Storage device

Patent metadata

Field	Value
Publication number	US-2020097171-A1
Application number	US-201916533883-A
Country	US
Kind code	A1
Filing date	Aug 7, 2019
Priority date	Sep 21, 2018
Publication date	Mar 26, 2020
Grant date	—

Abstract

A storage device includes a first memory device including a plurality of first memory cells, a second memory device including a plurality of second memory cells having the same type as the plurality of first memory cells, and a controller that communicates with the first memory device through a first memory interface and communicates with the second memory device through a second memory interface having an operating speed higher than an operating speed of the first memory interface.

First claim

1 . A storage device comprising:
a first memory device including a plurality of first memory cells; a second memory device including a plurality of second memory cells having a same type as the plurality of first memory cells; and a controller configured to communicate with the first memory device through a first memory interface and to communicate with the second memory device through a second memory interface having an operating speed higher than an operating speed of the first memory interface.

2 . The storage device of claim 1 , wherein each of the plurality of first memory cells and the plurality of second memory cells is a NAND flash memory cell.

3 . The storage device of claim 1 , wherein:
the first memory device operates in response to a first command latch enable signal, a first address latch enable signal, a first write enable signal, a first read enable signal, and a plurality of first data signals provided through the first memory interface, the second memory device operates in response to a second command latch enable signal, a second address latch enable signal, a second write enable signal, a second read enable signal, and a plurality of second data signals provided through the second memory interface, and a number of the plurality of second data signals is more than a number of the plurality of first data signals.

4 . The storage device of claim 1 , wherein:
the first memory device includes a plurality of first data signal pins connected with the first memory interface, the second memory device includes a plurality of second data signal pins connected with the second memory interface, and a number of the second data signal pins is more than a number of the first data signal pins.

5 . The storage device of claim 4 , wherein:
the plurality of first data signal pins are arranged in an edge area of the first memory device, and the plurality of second data signal pins are arranged in a center area of the second memory device.

6 . The storage device of claim 1 , wherein:
the plurality of first memory cells of the first memory device are divided into a plurality of first planes, the plurality of second memory cells of the second memory device are divided into a plurality of second planes, and a number of the second planes is more than a number of the first planes.

7 . The storage device of claim 1 , wherein a size of data exchanged through the second memory interface per unit time is greater than a size of data exchanged through the first memory interface per unit time.

8 . The storage device of claim 1 , wherein the second memory device includes a multiply and accumulate (MAC) engine configured to:
perform a MAC operation on data provided from the controller through the second memory interface and a weight stored in the plurality of second memory cells, and output a result of the MAC operation through the second memory interface.

9 . The storage device of claim 1 , wherein the controller includes:
a first memory interface circuit configured to communicate with the first memory device through the first memory interface; a second memory interface circuit configured to communicate with the second memory device through the second memory interface; a first processor configured to control the first memory interface circuit to perform an access operation on the first memory device; and a second processor configured to control the second memory interface circuit to perform an access operation on the second memory device.

10 . The storage device of claim 9 , wherein:
the first processor is further configured to store first user data provided from an external device in the first memory device or to provide second user data stored in the first memory device to the external device, and the second processor is further configured to perform a special operation on special data provided from the external device based on weight information stored in the second memory device and to provide a result of the special operation to the external device.

11 . The storage device of claim 1 , further comprising:
a third memory device including a plurality of third memory cells having a same type as the plurality of first memory cells and configured to communicate with the controller through the first memory interface, wherein: the first memory device communicates with the controller through a first channel of the first memory interface, and the third memory device communicates with the controller through a second channel of the first memory interface.

12 . The storage device of claim 1 , further comprising a third memory device including a plurality of third memory cells having a same type as the plurality of first memory cells and configured to communicate with the controller through a third memory interface.

13 . A storage device comprising:
a first controller configured to communicate with an external device through a host interface; a first memory device including a plurality of first memory cells, and configured to communicate with the first controller through a first channel of a first memory interface; a second memory device including a plurality of second memory cells having a same type as the plurality of first memory cells; and a second controller configured to communicate with the first controller through a second channel of the first memory interface and connected with the second memory device through a second memory interface.

14 . The storage device of claim 13 , wherein each of the plurality of first memory cells and the plurality of second memory cells is a NAND flash memory cell.

15 . The storage device of claim 13 , wherein:
the first memory device operates in response to a first command latch enable signal, a first address latch enable signal, a first write enable signal, a first read enable signal, and a plurality of first data signals provided through the first memory interface, the second memory device operates in response to a second command latch enable signal, a second address latch enable signal, a second write enable signal, a second read enable signal, and a plurality of second data signals provided through the second memory interface, and a number of the plurality of second data signals is more than a number of the plurality of first data signals.

16 . The storage device of claim 13 , wherein:
the first memory device includes a plurality of first data signal pins connected with the first memory interface, the second memory device includes a plurality of second data signal pins connected with the second memory interface, and a number of the second data signal pins is more than a number of the first data signal pins.

17 . The storage device of claim 13 , wherein:
the plurality of first memory cells of the first memory device are divided into a plurality of first planes, and the plurality of second memory cells of the second memory device are divided into a plurality of second planes, and a number of the second planes is more than a number of the first planes.

18 . The storage device of claim 13 , further comprising a third memory device including a plurality of third memory cells having a same type as the plurality of first memory cells and configured to communicate with the second controller through a third memory interface.

19 . A storage device comprising:
a first memory device including a plurality of first NAND flash memory cells; a second memory device including a plurality of second NAND flash memory cells; and a controller configured to

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Younggeon
• Seol Changkyu
• Kim Hyeonwu
• Song Hyeongseok

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title