Current Balance Feedback Circuit and Method to Improve the Stability of a Multi-Phase Converter

Patent metadata

Field	Value
Publication number	US-2020091819-A1
Application number	US-201816131799-A
Country	US
Kind code	A1
Filing date	Sep 14, 2018
Priority date	Sep 14, 2018
Publication date	Mar 19, 2020
Grant date	—

Abstract

A solution is provided for a current balance feedback method to improve stability in a multi-phase DC-DC switching converter, where the current balance feedback signal is added to the PWM duty signal, after the PWM comparator. Using this feedback method, current balance oscillation issues caused by the non-linearity of the main control loop can be solved, and provide better current balance stability in the switching converter. Advantages include improving the stability of the current balance feedback loop by introducing the correction post PW modulation in the time domain, effectively bypassing interaction with the PW modulator. The current balance feedback loop stability improvement reduces PCB design effort and iteration.

First claim

The invention claimed is:

1 . A current balance feedback circuit, in a multi-phase DC-DC switching converter, comprising:
a pulse width modulator, configured to provide a primary pulse width modulation signal to a first pulse expander; a current balance circuit, configured to compare a first phase current with a second phase current and to provide a current error signal to said first pulse expander; and said first pulse expander, coupled to said current balance circuit and to said pulse width modulator, wherein said first pulse expander is configured to add a delay in a turn-off time to said primary pulse width modulation signal output from a PWM comparator, and to produce a secondary pulse modulation signal, wherein said delay varies linearly with said current error signal.

2 . The current balance feedback circuit of claim 1 , wherein said primary pulse width modulation signal comprises a rising edge and a falling edge, and wherein said delay is added to said falling edge.

3 . The current balance feedback circuit of claim 1 , wherein said first pulse expander comprises said comparator for comparing said current error signal with a reference value.

4 . The current balance feedback circuit of claim 1 , wherein said current balance circuit is an analog circuit.

5 . The current balance feedback circuit of claim 1 , wherein said multi-phase DC-DC switching converter is a voltage mode switching converter.

6 . The current balance feedback circuit of claim 1 , wherein said multi-phase DC-DC switching converter is a current mode switching converter.

7 . The current balance feedback circuit of claim 1 , wherein said multi-phase DC-DC switching converter comprises a master phase and a slave phase, and wherein said secondary pulse modulation signal is used to control said slave phase.

8 . The current balance feedback circuit of claim 1 , wherein said multi-phase DC-DC switching converter comprises a master phase and a plurality of slave phases, wherein each of said plurality of slave phases includes one of said current balance feedback circuits.

9 . The current balance feedback circuit of claim 1 , wherein said secondary pulse modulation signal current is balanced between multiple inductors.

10 . The current balance feedback circuit of claim 7 , wherein said master phase further comprises a second pulse expander, configured to provide a fixed delay to control said master phase.

11 . The current balance feedback circuit of claim 10 , wherein a fixed signal is provided at an input to said second pulse expander.

12 . The current balance feedback circuit of claim 10 , wherein said second pulse expander has two inputs, both connected to ground.

13 . A method for current balance feedback, to improve stability of a multi-phase DC-DC switching converter, comprising:
providing a primary pulse width modulation signal with a pulse width modulator, to a first pulse expander; comparing a first phase current with a second phase current, with a current balance circuit, to provide a current error signal to said first pulse expander; and adding a delay in a turn-off time to the primary pulse width modulation signal, output from a pulse width modulation (PWM) comparator, using said first pulse expander, wherein a length of said delay is based on said current error signal, to provide a secondary pulse modulation signal.

14 . The method for current balance feedback of claim 13 , wherein said delay varies linearly with said current error signal.

15 . The method for current balance feedback of claim 13 , wherein said primary pulse width modulation signal comprises a rising edge and a falling edge, and adding said delay to said falling edge.

16 . The method for current balance feedback of claim 13 , wherein said PWM comparator compares said current error signal with a reference value.

17 . The method for current balance feedback of claim 13 , wherein said multi-phase DC-DC switching converter comprises a master phase and a slave phase, and wherein said secondary pulse modulation signal controls said slave phase.

18 . The method for current balance feedback of claim 13 , wherein said multi-phase DC-DC switching converter comprises a master phase and a plurality of slave phases, wherein each of said plurality of slave phases includes a current balance feedback circuit.

19 . The method for current balance feedback of claim 13 , wherein said secondary pulse modulation signal current is balanced between multiple inductors.

20 . The method for current balance feedback of claim 17 , wherein said master phase further comprises a second pulse expander, configured to provide a fixed delay to control said master phase.

21 . The method for current balance feedback of claim 20 , wherein a fixed signal is provided at an input to said second pulse expander.

22 . The method for current balance feedback of claim 20 , wherein said second pulse expander has two inputs, both connected to ground.

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Kobayashi Hidenori
• Ozawa Seiichi
• Kobayashi Daisuke

Classifications

• H02M3/1584

  with a plurality of power processing stages connected in parallel · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• H02M2001/0048

  Electricity · mapped topic

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title