Semiconductor device

Patent metadata

Field	Value
Publication number	US-2020091042-A1
Application number	US-201916543965-A
Country	US
Kind code	A1
Filing date	Aug 19, 2019
Priority date	Sep 18, 2018
Publication date	Mar 19, 2020
Grant date	—

Abstract

A semiconductor device may include a first conductor plate, a first semiconductor element that is a sole semiconductor element disposed on a main surface of the first conductor plate, an encapsulant encapsulating the first semiconductor element and a first power terminal connected to the first conductor plate within the encapsulant and projecting from the encapsulant along a first direction. The main surface of the first conductor plate may include a first side located close to the first power terminal and a second side located opposite the first side with respect to the first direction. With respect to the first direction, a distance from the first semiconductor element to the first side may be larger than a distance from the first semiconductor element to the second side.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first conductor plate; a first semiconductor element that is a sole semiconductor element disposed on a main surface of the first conductor plate; an encapsulant encapsulating the first semiconductor element; and a first power terminal connected to the first conductor plate within the encapsulant and projecting from the encapsulant along a first direction, wherein the main surface of the first conductor plate comprises a first side located close to the first power terminal and a second side located opposite the first side with respect to the first direction, and with respect to the first direction, a distance from the first semiconductor element to the first side is larger than a distance from the first semiconductor element to the second side.

2 . The semiconductor device according to claim 1 , wherein the distance from the first semiconductor element to the first side is equal to or larger than a half of a size of the first semiconductor element with respect to the first direction.

3 . The semiconductor device according to claim 1 , wherein with respect to the first direction, the distance from the first semiconductor element to the first side is at least twice the distance from the first semiconductor element to the second side.

4 . The semiconductor device according to claim 1 , further comprising a second conductor plate opposed to the first conductor plate with the first semiconductor element interposed therebetween,
wherein the second conductor plate comprises a main surface connected to the first semiconductor element within the encapsulant.

5 . The semiconductor device according to claim 4 , wherein
the main surface of the second conductor plate comprises a first side located close to the first power terminal and a second side located opposite the first side with respect to the first direction, and with respect to the first direction, a distance from the first semiconductor element to the first side of the second conductor plate is larger than a distance from the first semiconductor element to the second side of the second conductor plate.

6 . The semiconductor device according to claim 4 , further comprising:
a third conductor plate located side by side with the first conductor plate in a second direction perpendicular to the first direction; a second semiconductor element that is a sole semiconductor element disposed on a main surface of the third conductor plate within the encapsulant; and a second power terminal connected to the third conductor plate within the encapsulant and projecting from the encapsulant along the first direction, wherein the main surface of the third conductor plate comprises a first side located close to the second power terminal and a second side located opposite the first side with respect to the first direction, and with respect to the first direction, a distance from the second semiconductor element to the first side of the third conductor plate is larger than a distance from the second semiconductor element to the second side of the third conductor plate.

7 . The semiconductor device according to claim 6 , wherein
the third conductor plate is connected to the second conductor plate via a first connector portion located between the second conductor plate and the third conductor plate, and in a plan view along a direction perpendicular to the third conductor plate, at least a half of the first semiconductor element and at least a half of the second semiconductor element are each located within a region defined by virtually expanding the first connector portion in the second direction.

8 . The semiconductor device according to claim 7 , further comprising:
a fourth conductor plate opposed to the third conductor plate with the second semiconductor element interposed therebetween; and a third power terminal connected to the fourth conductor plate within the encapsulant and projecting from the encapsulant along the first direction, wherein the fourth conductor plate is located side by side with the second conductor plate in the second direction and is connected to the third power terminal via a second connector portion, and in a plan view along a direction perpendicular to the fourth conductor plate, the second connector portion is located between the second conductor plate and the fourth conductor plate and is further located between the third power terminal and the first connector portion.

9 . The semiconductor device according to claim 8 , wherein in the plan view along the direction perpendicular to the fourth conductor plate, neither the first semiconductor element nor the second semiconductor element is located within a region defined by virtually expanding the second connector portion in the second direction.

Assignees

• Toyota Motor Co Ltd

Inventors

• Kadoguchi Takuya
• Takahagi Satoshi

Classifications

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/016

  using moulds · CPC title