Information processing apparatus, parallel computer system, and method for control

Patent metadata

Field	Value
Publication number	US-2020076880-A1
Application number	US-201916538882-A
Country	US
Kind code	A1
Filing date	Aug 13, 2019
Priority date	Aug 28, 2018
Publication date	Mar 5, 2020
Grant date	—

Abstract

In a parallel computer system having multiple information processing apparatuses, a first information processing apparatus includes circuitry configured to wait for calculation target data from each of one or more other information processing apparatuses being included in the plurality of information processing apparatus; carry out an average calculation that calculates an average value of a plurality of calculation target data including the waited calculation target data; and transmit the calculated average value to a second information processing apparatus being one of the plurality of information processing apparatuses and being different from the other information processing apparatuses. This configuration makes it possible to achieve highly-precise collective average calculation without requiring bit expansion.

First claim

What is claimed is:

1 . An information processing apparatus among a plurality of information processing apparatuses constituting a parallel computer system, the information apparatus serving as a first information processing apparatus comprising:
circuitry configured to wait for calculation target data from each of one or more other information processing apparatuses being included in the plurality of information processing apparatus; carry out an average calculation that calculates an average value of a plurality of calculation target data including the waited calculation target data; and transmit the calculated average value to a second information processing apparatus being one of the plurality of information processing apparatuses and being different from the other information processing apparatuses.

2 . The information processing apparatus according to claim 1 , wherein the waited calculation target data from each of the one or more other information processing apparatuses is the average value calculated in the other information processing apparatus.

3 . The information processing apparatus according to claim 1 , wherein the transmitted average value is used as the calculation target data in the second information processing apparatus.

4 . The information processing apparatus according to claim 1 , wherein the circuitry carries out the average calculation by adding 2{circumflex over ( )}n of the calculation target data and extracting higher bits from a sum obtained by the adding through n-bit shift that removes n lower bits.

5 . The information processing apparatus according to claim 1 , further comprising at least one processor and at least one transmitter, wherein
the processor waits for the calculation target data and carries out the average calculation, and the transmitter transmits the calculated average value to the second information processing apparatus.

6 . The information processing apparatus according to claim 1 , further comprising a first processor and a second processor, wherein
the first processor waits for the calculation target data and the second processor carries out the average calculation.

7 . A parallel computer system comprising a plurality of information processing apparatuses, a first information processing apparatus among the plurality of information processing apparatus comprising:
circuitry configured to wait for calculation target data from each of one or more other information processing apparatuses being included in the plurality of information processing apparatus; carry out an average calculation that calculates an average value of a plurality of calculation target data including the waited target data waited; and transmit the calculated average value to a second information processing apparatus being one of the plurality of information processing apparatuses and being different from the other information processing apparatuses.

8 . The parallel computer system according to claim 7 , wherein the calculation target data from each of the one or more other information processing apparatuses is the average value calculated in the other information processing apparatus.

9 . The parallel computer system according to claim 7 , wherein the second information processing apparatus uses the transmitted average value as the calculation target data.

10 . The parallel computer system according to claim 7 , wherein the circuitry carries out the average calculation by adding 2{circumflex over ( )}n of the calculation target data and extracting higher bits from a sum obtained by the adding through n-bit shift that removes n lower bits.

11 . The parallel computer system according to claim 7 , wherein the first information processing apparatus comprises at least one processor and at least one transmitter, and
the processor waits for the calculation target data and carries out the average calculation, and the transmitter transmits the calculated average value to the second information processing apparatus.

12 . The parallel computer system according to claim 7 , wherein the first information processing apparatus comprises a first processor and a second processor, and
the first processor waits for the calculation target data and the second processor carries out the average calculation.

13 . A method for controlling an information processing apparatus among a plurality of information processing apparatus constituting a parallel computer system, the method comprising:
at a first information processing apparatus among the plurality of the information processing apparatus, waiting for calculation target data from each of one or more other information processing apparatuses being included in the plurality of information processing apparatus; carrying out an average calculation that calculates an average value of a plurality of calculation target data including the calculation target data waited in the waiting; and transmitting the average value calculated in the average calculation to a second information processing apparatus being one of the plurality of information processing apparatuses and being different from the other information processing apparatuses.

14 . The method according to claim 13 , wherein the calculation target data from each of the one or more other information processing apparatuses, the waited calculation target data, is the average value calculated in the other information processing apparatus.

15 . The method according to claim 13 , wherein the transmitted average value is used as the calculation target data in the second information processing apparatus.

16 . The method according to claim 13 , wherein the average calculation is carried out by adding 2{circumflex over ( )}n of the calculation target data and extracting higher bits from a sum obtained by the adding through n-bit shift that removes n lower bits.

17 . The method according to claim 13 , wherein the first information processing apparatus further comprises at least one processor and at least one transmitter, and
the processor waits for the calculation target data and carries out the average calculation, and the transmitter transmits the calculated average value to the second information processing apparatus.

18 . The method according to claim 13 , wherein the first information processing apparatus further comprises a first processor and a second processor, and
the first processor waits for the calculation target data and the second processor carries out the average calculation.

Assignees

• Fujitsu Ltd

Inventors

• Kondo Yuji
• Arakawa Takashi

Classifications

• H04L67/10 Primary

  in which an application is distributed across nodes in the network (software deployment G06F8/60; multiprogramming arrangements G06F9/46) · CPC title

• G06F15/17325

  Synchronisation; Hardware support therefor (intertask synchronisation G06F9/52) · CPC title

• G06F15/17306

  Intercommunication techniques · CPC title

• G06F9/546

  Message passing systems or structures, e.g. queues · CPC title

• G06F9/522

  Barrier synchronisation · CPC title