Apparatus and system of a low-voltage detector

Patent metadata

Field	Value
Publication number	US-2020072878-A1
Application number	US-201816122011-A
Country	US
Kind code	A1
Filing date	Sep 5, 2018
Priority date	Sep 5, 2018
Publication date	Mar 5, 2020
Grant date	—

Abstract

Some demonstrative embodiments include an apparatus including a low-voltage detector to detect whether a voltage difference between a first voltage of a first voltage domain and a second voltage of the first voltage domain is lower than a predefined voltage.

First claim

1 . An apparatus comprising a low-voltage detector to detect whether a voltage difference between a first voltage of a first voltage domain and a second voltage of the first voltage domain is lower than a predefined voltage, the low-voltage detector comprising:
a first current generator configured to generate a first reference current based on a difference between the first voltage of the first voltage domain and the second voltage of the first voltage domain; a second current generator configured to generate a second reference current based on a difference between a voltage of a second voltage domain and a reference voltage; and a detector component to detect whether the voltage difference is lower than the predefined voltage based on the first reference current and the second reference current, wherein the detector component comprises a current mirror configured to generate a mirrored reference current based on the first reference current, the detector component configured to detect whether the voltage difference is lower than the predefined voltage based on a comparison between the mirrored reference current and the second reference current.

2 . The apparatus of claim 1 , wherein the detector component is configured to detect whether the voltage difference is lower than the predefined voltage, when the first voltage domain is at a switching mode and the second voltage domain is at a fixed mode.

3 . The apparatus of claim 1 comprising a first switch coupled to the second voltage of the first voltage domain and a second switch coupled to the second voltage of the first voltage domain, the detector component configured to detect whether the voltage difference is lower than the predefined voltage, when the first switch is at an on-state and the second switch is at an off-state.

4 . The apparatus of claim 3 , wherein the detector component is configured to, upon detection that the voltage difference is lower than the predefined voltage, trigger at least one of switching off the first switch or switching on the second switch.

5 . The apparatus of claim 1 , wherein the low-voltage detector comprises a high-side Under Voltage Lock Out (UVLO).

6 . The apparatus of claim 1 , wherein the detector component comprises a comparison node between the current mirror and the second current generator, the comparison node to provide a current difference between the mirrored reference current and the second reference current.

7 . The apparatus of claim 6 , wherein the detector component comprises a comparison buffer to receive the current difference from the comparison node, and, based on the current difference, to output a signal to indicate that the voltage difference is lower than the predefined voltage.

8 . The apparatus of claim 7 , wherein the detector component comprises a three state buffer coupled between the comparison node and an output of the comparison buffer, the three state buffer configured to latch the comparison node to the output of the comparison buffer based on a detection of a transient event in the first voltage domain.

9 . The apparatus of claim 8 comprising a transient detection circuit configured to detect the transient event, and, based on a detection of the transient event, to provide a transient signal to an input of the three state buffer.

10 . The apparatus of claim 1 , wherein the first current generator comprises a first metal-oxide-semiconductor (MOS) transistor, and the second current generator comprises a second MOS transistor, the first reference current is driven via a drain of the first MOS transistor and the second reference current is driven via a drain of the second MOS transistor.

11 . The apparatus of claim 10 , wherein the first current generator comprises a high voltage transistor configured to prevent a voltage stress over the first MOS transistor, a source of the high voltage transistor is coupled to the drain of the first MOS transistor.

12 . The apparatus of claim 11 , wherein a gate of the high voltage transistor is coupled to a reference voltage of the first voltage domain.

13 . The apparatus of claim 11 , wherein a gate of the high voltage transistor is coupled to the second voltage of the first voltage domain.

14 . The apparatus of claim 10 , wherein the first current generator comprises a voltage clamping component configured to clamp a voltage of the drain of the first MOS transistor.

15 . The apparatus of claim 14 , wherein the voltage clamping component is configured to clamp the voltage of the drain of the first MOS transistor to a difference between a reference voltage of the first voltage domain and a drain voltage of the first MOS transistor, the voltage clamping component is between the drain of the first MOS transistor and the reference voltage of the first voltage domain.

16 . The apparatus of claim 14 , wherein the voltage clamping component is configured to clamp the voltage of the drain of the first MOS transistor to a difference between the second voltage of the first voltage domain and a drain voltage of the first MOS transistor, the voltage clamping component is between the drain of the first MOS transistor and the second voltage of the first voltage domain.

17 . The apparatus of claim 10 , wherein the first current generator comprises first and second loads coupled in series between the first voltage of the first voltage domain and the second voltage of the first voltage domain, and a third load between the first voltage of the first voltage domain and a source of the first MOS transistor, the second current generator comprises a fourth load between the first voltage of the second voltage domain and a source of the second MOS transistor.

18 . The apparatus of claim 17 , wherein a gate voltage of the first MOS transistor comprises a voltage at a node between the first and second loads, and a gate voltage of the second MOS transistor comprises the reference voltage.

19 . The apparatus of claim 17 , wherein the first and second loads are equal, the third and fourth loads are equal, and the first and second MOS transistors are identical.

20 . The apparatus of claim 1 , wherein the first voltage domain comprises a high-side voltage domain, and the second voltage domain comprises a low-side voltage domain.

21 . The apparatus of claim 1 , wherein the first voltage of the first voltage domain comprises a BOOT voltage, the second voltage of the first voltage domain comprises a switching (SW) voltage, the voltage of the second voltage domain comprises a drain-drain voltage (VDD), and the reference voltage comprises a bandgap voltage.

22 . An electronic device comprising:
a DC to DC (DC-DC) converter comprising:
a first driver to drive a first switch based on a first voltage of a first voltage domain and a second voltage of the first voltage domain;
a second driver to drive a second switch based on a first voltage of a second voltage domain and a second voltage of the second voltage domain; and
a low-voltage detector to detect whether a voltage difference between the first voltage of the first voltage domain and the second voltage of the first voltage domain is lower than a predefined voltage, the low-voltage detector comprising:
a first current generator configured to generate a first reference current based on a difference between the first voltage of the first voltage domain and the second voltage of the first voltage domain;
a second current generator configured to generate a second reference current based on a

Assignees

• Tower Semiconductor Ltd

Inventors

• Pollak Dan
• Lerner Valentin
• Brandelstein Sharkaz Sharon

Classifications

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M1/32 Primary

  Means for protecting converters other than automatic disconnection · CPC title

• G01R19/16519 Primary

  using FET's · CPC title

• H03K17/08122

  in field-effect transistor switches · CPC title