Mesa trench etch with stacked sidewall passivation

Patent metadata

Field	Value
Publication number	US-2020052012-A1
Application number	US-201816057191-A
Country	US
Kind code	A1
Filing date	Aug 7, 2018
Priority date	Aug 7, 2018
Publication date	Feb 13, 2020
Grant date	—

Abstract

A method of forming an array of photodiodes includes forming a cap layer on a surface of an absorption layer. The method includes forming a plurality of spaced apart pixel diffusion areas in the cap layer. The method includes forming a mesa trench with opposed sidewalls through the cap layer, wherein the mesa trench surrounds each of the pixel diffusion areas separating the pixel diffusion areas from one another. The method includes forming a sidewall passivation layer over the sidewalls of the mesa trench and removing a portion of the sidewall passivation layer to expose a respective contact electrically connected to each of the pixel diffusion areas, but leaving the sidewalls of the mesa trench covered with the sidewall passivation layer wherein the contact is open and uncovered for electrical connection.

First claim

What is claimed is:

1 . A method of forming an array of photodiodes comprising:
forming a cap layer on a surface of an absorption layer; forming a plurality of spaced apart pixel diffusion areas in the cap layer, wherein each pixel diffusion area extends beyond the surface of the absorption layer and into the absorption layer to receive a charge generated from photons received through the absorption layer by the pixel diffusion area; forming a mesa trench with opposed sidewalls through the cap layer, wherein the mesa trench surrounds each of the pixel diffusion areas separating the pixel diffusion areas from one another; forming a sidewall passivation layer over the sidewalls of the mesa trench; and removing a portion of the sidewall passivation layer to expose a respective contact electrically connected to each of the pixel diffusion areas, but leaving the sidewalls of the mesa trench covered with the sidewall passivation layer wherein the contact is open and uncovered for electrical connection.

2 . The method as recited in claim 1 , further comprising forming the contacts electrically connected to the respective pixel diffusion areas so each contact passes through a passivation layer to make electrical contact with the respective pixel diffusion area.

3 . The method as recited in claim 1 , wherein forming the mesa trench includes forming the mesa trench completely through the cap layer and partially or completely through the absorption layer.

4 . The method as recited in claim 1 , wherein forming the mesa trench includes forming the mesa by dry etching followed by wet etching.

5 . The method as recited in claim 1 , wherein forming the sidewall passivation layer includes covering the contacts and the mesa sidewalls with the sidewall passivation layer, and wherein removing the portion of the passivation layer includes covering the sidewall passivation layer with a patterned photoresist layer and removing portions of the sidewall passivation layer not protected by the photoresist layer.

6 . The method as recited in claim 1 , further comprising disposing the absorption layer on a buffer layer that is on a substrate layer on an opposite side of the absorption layer from the cap layer.

7 . A photodiode array comprising:
an absorption layer; a cap layer disposed on a surface of the absorption layer; a plurality of pixel diffusion areas within the cap layer, each of the pixel diffusion areas of the plurality of pixel diffusion areas extending beyond the surface of the absorption layer and into the absorption layer to receive a charge generated from photons received through the absorption layer by the respective pixel diffusion area, wherein a mesa trench is defined through the cap layer surrounding each of the pixel diffusion areas in the plurality of pixel diffusion areas, wherein the mesa trench defines sidewalls; and a sidewall passivation layer that covers the sidewalls of the mesa trench, wherein openings through the sidewall passivation layer are included to leave open a contact for each pixel diffusion area in the plurality of pixel diffusion areas for electrical connection.

8 . The photodiode array as recited in claim 7 , wherein the sidewall passivation layer includes multiple dielectric layers, configured to reduce dark current due to surface leakage and to reduce stress.

9 . The photodiode array as recited in claim 7 , wherein the absorption layer includes a semiconductor material able to detect optical signals from a light source through wavelengths ranging from the visible region to the infrared region.

10 . The photodiode array as recited in claim 7 , further comprising a passivation layer disposed on a surface of the cap layer opposite from the absorption layer, wherein the passivation layer forms a portion of the side walls of the mesa trench.

11 . The photodiode array as recited in claim 9 , wherein the contact for each of the pixel diffusion areas of the plurality of pixel diffusion areas is disposed on the passivation layer and in electrical contact with the pixel diffusion area through an opening in the passivation layer.

12 . The photodiode array as recited in claim 11 , wherein a portion of the contact is sandwiched between the sidewall passivation layer and the passivation layer.

13 . The photodiode array as recited in claim 7 , wherein the mesa extends completely though the cap layer and completely or partially through the absorption layer.

14 . The photodiode array as recited in claim 7 , further comprising a substrate layer on a side of absorption layer opposite the cap layer.

15 . The photodiode array as recited in claim 14 , further comprising a buffer layer disposed between the absorption layer and the substrate layer.

16 . The photodiode array as recited in claim 7 , wherein the cap layer includes InP and wherein the absorption layer includes InGaAs.

17 . The photodiode array as recited in claim 7 , wherein the sidewall passivation layer combined with a space gap of the mesa trench reflects photons that hit the sidewall passivation layer back into the absorption layer within a desired wavelength range for increased quantum efficiency relative to if there were no sidewall passivation layer and space gap.

18 . The photodiode array as recited in claim 7 , wherein the sidewalls have an angle relative to one another, wherein the angle is tailored using inductive coupled plasma (ICP) design of experiment (DOE).

Assignees

• Sensors Unlimited Inc

Inventors

• Zhang Wei
• Evans Michael J
• Malchow Douglas Stewart
• Bereznycky Paul L
• Paik Namwoong

Classifications

• H01L27/1463

  Electricity · mapped topic

• H01L27/14636

  Electricity · mapped topic

• H01L27/1461 Primary

  Electricity · mapped topic

• H01L27/14694

  Electricity · mapped topic

• H01L27/14685

  Electricity · mapped topic