Method for manufacturing oxide semiconductor device

Patent metadata

Field	Value
Publication number	US-2020052003-A1
Application number	US-201916546469-A
Country	US
Kind code	A1
Filing date	Aug 21, 2019
Priority date	Jul 31, 2009
Publication date	Feb 13, 2020
Grant date	—

Abstract

An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

First claim

1 . (canceled)

2 . A display device comprising:
a pixel, the pixel comprising:
a first conductive layer over and in contact with a substrate;
a first insulating layer over the first conductive layer;
a first oxide semiconductor layer over and in contact with the first insulating layer, the first oxide semiconductor layer comprising a channel formation region;

a second oxide semiconductor layer over and in contact with the first oxide semiconductor layer;
an oxide insulating layer over and in contact with a top surface and a side surface of the first oxide semiconductor layer, the oxide insulating layer comprising a first contact hole;
a second conductive layer over the oxide insulating layer, the second conductive layer in contact with the first oxide semiconductor layer through the first contact hole;
a third conductive layer over and in contact with the second oxide semiconductor layer,
a second insulating layer over the first oxide semiconductor layer, the second conductive layer, the second oxide semiconductor layer and the third conductive layer,
a planarization layer over the second insulating layer; and
a pixel electrode over the planarization layer,
wherein the pixel electrode overlaps the first conductive layer, the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein the second conductive layer and the third conductive layer comprise the same material,
wherein the pixel electrode is in contact with the second conductive layer through a second contact hole in the second insulating layer and a third contact hole in the planarization layer, and
wherein the second oxide semiconductor layer overlaps the first conductive layer with the first insulating layer therebetween to form a storage capacitor.

3 . The display device according to claim 2 ,
wherein the first insulating layer comprises a first layer and a second layer over and in contact with the first layer, wherein the first layer is a silicon oxide layer, and wherein the second layer is a silicon nitride layer.

4 . The display device according to claim 2 ,
wherein the oxide insulating layer overlaps with the channel formation region in the first oxide semiconductor layer.

5 . The display device according to claim 2 , further comprising:
a fourth conductive layer over and in contact with the substrate, wherein the channel formation region in the first oxide semiconductor layer overlaps the fourth conductive layer.

5 . The display device according to claim 5 ,
wherein the first conductive layer and the fourth conductive layer comprise the same material.

6 . The method for manufacturing the semiconductor device according to claim 2 , wherein the first contact hole completely overlaps with the first oxide semiconductor layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Ohara Hiroki
• Sasaki Toshinari
• Noda Kosei
• Kuwabara Hideaki

Classifications

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• G02F1/136277

  formed on a semiconductor substrate, e.g. of silicon · CPC title

• G02F1/1337

  Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title