Method for Producing a Semiconductor Component

Patent metadata

Field	Value
Publication number	US-2020027969-A1
Application number	US-201916514292-A
Country	US
Kind code	A1
Filing date	Jul 17, 2019
Priority date	Jul 18, 2018
Publication date	Jan 23, 2020
Grant date	—

Abstract

A method for producing a semiconductor component includes: providing a semiconductor body having a first dopant of a first conductivity type; forming a first trench in the semiconductor body starting from a first side; filling the first trench with a semiconductor filler material; forming a superjunction structure by introducing a second dopant of a second conductivity type into the semiconductor body, the semiconductor filler material being doped with the second dopant; forming a second trench in the semiconductor body starting from the first side; and forming a trench structure in the second trench.

First claim

What is claimed is:

1 . A method for producing a semiconductor component, the method comprising:
providing a semiconductor body having a first dopant of a first conductivity type; forming a first trench in the semiconductor body starting from a first side; filling the first trench with a semiconductor filler material; forming a superjunction structure by introducing a second dopant of a second conductivity type into the semiconductor body, the semiconductor filler material being doped with the second dopant; forming a second trench in the semiconductor body starting from the first side; and forming a trench structure in the second trench.

2 . The method of claim 1 , wherein the second dopant partially compensates for a concentration of the first dopant.

3 . The method of claim 1 , wherein the first dopant is introduced into the semiconductor body by a plurality of ion implantations with different implantation energies or by in-situ doping.

4 . The method of claim 3 , wherein the first dopant is introduced into the semiconductor body by the plurality of ion implantations with different implantation energies, such that a spacing of neighboring implantation peaks in a vertical direction lies in a range of 100 nm to 400 nm.

5 . The method of claim 3 , wherein a maximum implantation energy and a minimum implantation are selected such that a vertical spacing of the associated implantation peaks lies in a range of 1 μm to 3 μm.

6 . The method of claim 3 , further comprising:
introducing a non-doping element into the semiconductor body in addition to the first dopant, the non-doping element being configured to reduce diffusion of the first dopant due to a thermal budget.

7 . The method of claim 6 , wherein the non-doping element is carbon.

8 . The method of claim 7 , wherein the carbon is introduced into the semiconductor body by in-situ doping or by one or more ion implantations.

9 . The method of claim 1 , wherein the second dopant is introduced fully without masking, through a surface of an active transistor cell area by a plurality of ion implantations with different implantation energies.

10 . The method of claim 1 , wherein the first dopant is introduced fully without masking, through a surface of an active transistor cell area by a plurality of ion implantations with different implantation energies.

11 . The method of claim 1 , further comprising:
introducing carbon fully without masking, through a surface of an active transistor cell area by one or more ion implantations.

12 . The method of claim 1 , wherein the superjunction structure comprises a first region of the first conductivity type, in which there is partial compensation for the doping of the first dopant by the second dopant, and a neighboring second region of the second conductivity type, which comprises the semiconductor filler material and is doped with the second dopant, and wherein a dose of the first dopant along a segment differs by at most 5 % from a dose of the second dopant along the same segment, the segment passing fully through the first region and the second region in a first lateral direction.

13 . The method of claim 12 , wherein a width of the second trench along the first lateral direction is less than a width of the second region along the first lateral direction.

14 . The method of claim 1 , wherein forming the trench structure comprises:
lining the second trench with a dielectric structure which is configured at least partially as a gate dielectric; and forming a gate electrode material in the second trench.

15 . The method of claim 1 , wherein forming the second trench in the semiconductor body comprises:
a dry etching process; and after the dry etching process, wet etching with an alkaline solution.

16 . The method of claim 1 , further comprising:
enlarging the semiconductor body by forming a semiconductor layer on the first side after filling the first trench.

17 . The method of claim 1 , wherein the second trench is formed less deeply into the semiconductor body than the first trench.

Assignees

• Infineon Technologies Ag

Inventors

• Schloesser Till
• Kampen Christian
• Meiser Andreas

Classifications

• H10P14/3451

  Structure · CPC title

• H01L21/02587

  Electricity · mapped topic

• H01L29/66734 Primary

  Electricity · mapped topic

• H01L29/0634

  Electricity · mapped topic

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title