Memory Circuit and Cache Circuit Configuration

Patent metadata

Field	Value
Publication number	US-2020026648-A1
Application number	US-201916587215-A
Country	US
Kind code	A1
Filing date	Sep 30, 2019
Priority date	Nov 2, 2012
Publication date	Jan 23, 2020
Grant date	—

Abstract

A memory circuit includes a first memory circuit formed of a first die or a set of stacked dies. The memory circuit further includes a second memory circuit formed of a second die, the second memory circuit comprising one or more sets of memory cells of a second type and each set of the memory cells of the second type comprising multiple cache sections. The first die or the set of stacked dies are stacked over the second die, wherein the second die further includes a first plurality of I/O terminals and a second plurality of I/O terminals, the first plurality of I/O terminals being electrically coupled to the first memory circuit, and the second plurality of I/O terminals being electrically isolated from the first memory circuit.

First claim

What is claimed is:

1 . A memory circuit, comprising:
a first memory circuit formed of a first die or a set of stacked dies, the first memory circuit comprising multiple sets of memory cells of a first type; and a second memory circuit formed of a second die, the second memory circuit comprising one or more sets of memory cells of a second type and each set of the memory cells of the second type comprising multiple cache sections, each cache section associated with a corresponding one of the multiple sets of memory cells of the first type, the first die or the set of stacked dies being stacked over the second die, wherein the second die further includes a first plurality of I/O terminals and a second plurality of I/O terminals, the first plurality of I/O terminals being electrically coupled to the first memory circuit, and the second plurality of I/O terminals being electrically isolated from the first memory circuit and disposed such that at least one terminal of the second plurality of I/O terminals is between each terminal of the first plurality of I/O terminals and one of the multiple cache sections.

2 . The memory circuit of claim 1 , further comprising:
a memory controller circuit electrically coupled with the first memory circuit through the second die, the memory controller circuit being configured to access the multiple sets of memory cells of the first type.

3 . The memory circuit of claim 2 , further comprising:
a cache controller circuit electrically coupled with the memory controller circuit and the second memory circuit, the cache controller circuit being configured to receive a read command for reading requested data stored in the first memory circuit at a read address and to retrieve a valid duplication of the requested data from the second memory circuit if the valid duplication of the requested data exists in the second memory circuit.

4 . The memory circuit of claim 3 , wherein the cache controller circuit is further configured to write data corresponding to a write address to the first memory circuit in response to a write command received by the cache controller circuit.

5 . The memory circuit of claim 4 , wherein the cache controller circuit is further configured to invalidate a duplication of data stored in the second memory circuit corresponding to the write address.

6 . The memory circuit of claim 3 , wherein the cache controller circuit is further configured to bypass the second memory circuit in response to an external request.

7 . The memory circuit of claim 1 , wherein the memory cells of the second type are readable at a speed faster than the memory cells of the first type.

8 . The memory circuit of claim 1 , wherein the memory cells of the first type are dynamic random-access memory (DRAM) cells, and the memory cells of the second type are static random-access memory (SRAM) cells.

9 . The memory circuit of claim 1 , wherein the first plurality of I/O terminals is electrically coupled to the first memory circuit by through-silicon vias.

10 . The memory circuit of claim 1 , wherein the first plurality of I/O terminals and the second plurality of I/O terminals are disposed between the multiple cache sections.

11 . The memory circuit of claim 1 , wherein the second memory circuit has a top surface directly facing the first memory circuit and a bottom surface opposing the top surface, and wherein the first plurality of I/O terminals and the second plurality of I/O terminals are disposed on the bottom surface.

12 . A cache memory die, comprising:
a substrate; a predetermined number of sets of memory cells on the substrate; a first set of input/output terminals on a first surface of the cache memory die, the first set of input/output terminals configured to be coupled to a primary memory circuit outside the cache memory die, wherein the primary memory circuit is on a die different from the cache memory die; and a second set of input/output terminals on a second surface of the cache memory die, a first portion of the second set of input/output terminals being pin-to-pin compatible with the first set of input/output terminals, and a second portion of the second set of input/output terminals being not corresponding to any input/output terminal on the first surface of the cache memory die, wherein the second portion of the second set of input/output terminals is disposed between the first portion and the sets of memory cells.

13 . The cache memory die of claim 12 , wherein the second portion of the second set of input/output terminals is disposed around the first portion of the second set of input/output terminals.

14 . The cache memory die of claim 12 , wherein the second set of input/output terminals is disposed between the sets of memory cells.

15 . The cache memory die of claim 12 , wherein the memory cells are static random-access memory (SRAM) cells.

16 . The cache memory die of claim 12 , wherein the substrate comprises a plurality of through-silicon vias, the plurality of through-silicon vias electrically coupling the first set of input/output terminals and the first portion of the second set of input/output terminals.

17 . A cache circuit, comprising:
a first die, comprising: a predetermined number of sets of memory cells; a first set of terminals on a first surface of the first die, the first set of terminals being configured to be coupled to a primary memory circuit outside the cache circuit, wherein the primary memory circuit is on a die or a stack of dies different from the first die; a second set of terminals on a second surface of the first die, a first portion of the second set of terminals being pin-to-pin compatible with the first set of terminals and a second portion of the second set of terminals not being configured for electrical coupling to the primary memory circuit, wherein the second portion is disposed at a periphery of the first portion; and a second die comprising a memory controller circuit in communication with the primary memory circuit through the first die.

18 . The cache circuit of claim 17 , wherein the second die is electrically coupled with the first die through the second portion of the second set of terminals.

19 . The cache circuit of claim 17 , wherein the memory cells are static random-access memory (SRAM) cells.

20 . The cache circuit of claim 17 , wherein the second die is disposed on the second surface of the first die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Hsien-Hsin Sean
• Shen William Wu
• Lee Yun-Han

Classifications

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G09F7/14

  Constructional features of the symbol bearing or forming elements · CPC title

• G09F7/16

  Letters, numerals, or other symbols adapted for permanent fixing to a support · CPC title

• G09B21/004 Primary

  Details of particular tactile cells, e.g. electro-mechanical or mechanical layout · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title