Integrated CMOS Source Drain Formation With Advanced Control

Patent metadata

Field	Value
Publication number	US-2020013878-A1
Application number	US-201916502555-A
Country	US
Kind code	A1
Filing date	Jul 3, 2019
Priority date	Jul 5, 2018
Publication date	Jan 9, 2020
Grant date	—

Abstract

A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

First claim

What is claimed is:

1 . A method of forming a semiconductor device, the method comprising:
performing an anisotropic etch process on a semiconductor material on a semiconductor substrate to expose a surface in the semiconductor material, the surface disposed between an existing structure of the semiconductor device and a bulk semiconductor portion of the semiconductor substrate on which the semiconductor material is formed; performing an isotropic etch process on an exposed sidewall to recess the semiconductor material that is disposed between the existing structure and the bulk semiconductor portion of the semiconductor substrate by a distance to form a cavity; and forming a layer of deposited material via a selective epitaxial growth (SEG) process on a surface of the cavity, the substrate not subjected to a pre-clean process between formation of the cavity and SEG.

2 . The method of claim 1 , wherein the isotropic etch occurs in a first process chamber and the method further comprises moving the substrate from the first process chamber to a second process chamber for the SEG process.

3 . The method of claim 2 , further comprising determining the distance that the semiconductor material has been recessed after isotropic etch and prior to the SEG process.

4 . The method of claim 3 , further comprising adjusting the SEG process based on the distance that the semiconductor material has been recessed.

5 . The method of claim 4 , further comprising epitaxial growing a portion of the semiconductor material prior to forming the layer of deposited material.

6 . The method of claim 3 , wherein the distance that the semiconductor material has been recessed comprises refractometry.

7 . The method of claim 3 , wherein the isotropic etch process comprises an etch process selective to the semiconductor material.

8 . The method of claim 7 , wherein the isotropic etch process comprises a chemical vapor etch process that includes exposing the exposed sidewall to at least one of HCl, GeH 4 or and Cl 2 .

9 . The method of claim 3 , wherein forming the layer of deposited material comprises filling the cavity with the deposited material.

10 . The method of claim 3 , further comprising, prior to forming the layer of deposited material, depositing a carbon-containing material on the surface of the cavity, wherein the carbon-containing material includes a silicon-carbon-phosphorus (SiCP) material.

11 . The method of claim 10 , wherein the SiCP material includes in the range of about 0.1 to 2.0 atomic percent carbon and in the range of about about 1×10 20 atoms/cm 3 to 1×10 21 atoms/cm 3 phosphorus.

12 . The method of claim 3 , wherein performing the isotropic etch process on the exposed sidewall to form the cavity in the semiconductor material comprises removing semiconductor material until a portion of the semiconductor material that comprises a phosphorus-doped bulk semiconductor material is exposed.

13 . The method of claim 3 , wherein the deposited material comprises an n-type dopant comprising arsenic (As), and the selective epitaxial growth (SEG) process includes exposing the surface of the cavity to at least one of AsCl 3 , TBA, or AsH 3 and at least one of dichlorosilane (DCS), HCl, SiH 4 , Si 2 H 6 , or Si 4 H 10 .

14 . The method of claim 13 , wherein forming the layer of deposited material comprises filling the cavity with arsenic-doped material having an arsenic concentration sufficient to produce a targeted tensile strain within the deposited material.

15 . The method of claim 3 , wherein the deposited material comprises a p-type dopant comprising boron (B), and the selective epitaxial growth (SEG) process includes exposing the surface of the cavity to one or more of borane, diborane or plasmas thereof.

16 . The method of claim 3 , further comprising forming a layer of additional deposited material via a selective epitaxial growth (SEG) process on a portion of the semiconductor material on which the anisotropic etch process is not performed, wherein the additional deposited material includes silicon (Si) and phosphorus (P).

17 . The method of claim 16 , wherein the layer of additional deposited material is formed without exposing the layer of deposited material formed on the surface of the cavity to air.

18 . The method of claim 1 , wherein the isotropic etch process and the SEG process are performed in the same platform under vacuum processing.

19 . A method of forming a semiconductor device, the method comprising:
positioning a semiconductor substrate with a semiconductor material thereon in a first processing chamber; performing an anisotropic etch process on the semiconductor material to expose a surface in the semiconductor material, the surface disposed between an existing structure of the semiconductor device and a bulk semiconductor portion of the semiconductor substrate on which the semiconductor material is formed; performing an isotropic etch process on an exposed sidewall to recess the semiconductor material that is disposed between the existing structure and the bulk semiconductor portion of the semiconductor substrate by a distance to form a cavity; moving the semiconductor substrate from the first processing chamber to a second processing chamber without exposing the semiconductor substrate to oxidative conditions; determining a distance that the semiconductor material has been recessed after isotropic etch; and forming a layer of deposited material in the second processing chamber using a selective epitaxial growth (SEG) process on a surface of the cavity, the semiconductor substrate not subjected to a pre-clean process between formation of the cavity and SEG, the SEG process accounting for the distance that the semiconductor material has been recessed after isotropic etch.

20 . A processing tool for forming a semiconductor device, the processing tool comprising:
a central transfer station having a plurality of processing chambers disposed around the central transfer station; a robot within the central transfer station configured to move a substrate between the plurality of processing chambers; a first processing chamber connected to the central transfer station, the first processing chamber configured to perform an isotropic etch process; a metrology station within the processing tool accessible to the robot, the metrology station configured to determine a distance of recess of semiconductor material on a substrate from the isotropic etch process; a second processing chamber connected to the central transfer station, the second processing chamber configured to perform a selective epitaxial growth (SEG) process; and a controller connected to one or more of the central transfer station, the robot, the first processing chamber, the metrology station or the second processing chamber, the controller having one or more configurations selected from a first configuration to move a substrate on the robot between the plurality of processing chambers and metrology station; a second configuration to perform an isotropic etch process on a substrate in the first processing chamber; a third configuration to perform an analysis to determine the recess of the semiconductor material in the metrology station; or a fourth configuration to perform a selective epitaxial growth process in the second processing chamber, the selective epitaxial growth process adjusted for the recess of the semiconductor material.

Assignees

• Applied Materials Inc

Inventors

• Colombeau Benjamin
• Mandrekar Tushar
• Liu Patricia M
• Parikh Suketu Arun
• Bauer Matthias
• Kioussis Dimitri R
• Natarajan Sanjay
• Dube Abhishek

Classifications

• H10P72/7602

  the wafers being placed on a robot blade or gripped by a gripper for conveyance · CPC title

• H10P72/3302

  Mechanical parts of transfer devices · CPC title

• H10P72/0604

  Process monitoring, e.g. flow or thickness monitoring · CPC title

• H10P72/0464

  characterised by the construction of the transfer chamber · CPC title

• H10P72/0454

  surrounding a central transfer chamber · CPC title