Guaranteed Data Compression

Patent metadata

Field	Value
Publication number	US-2020007149-A1
Application number	US-201916457266-A
Country	US
Kind code	A1
Filing date	Jun 28, 2019
Priority date	Jun 29, 2018
Publication date	Jan 2, 2020
Grant date	—

Abstract

Methods for converting an n-bit number into an m-bit number for situations where n>m and also for situations where n<m, where n and m are integers. The methods use truncation or bit replication followed by the calculation of an adjustment value which is applied to the replicated number.

First claim

What is claimed is:

1 . A method of mapping an input n-bit number to an output m-bit number, where n and m are integers and n>m, the method comprising:
truncating, in a truncation hardware unit, the input n-bit number from n-bits to m-bits to form an intermediate m-bit number; in a look-up logic hardware unit: (i) comparing pre-determined subsets of the bits of the input n-bit number with pre-determined values in fixed-function circuitry, and (ii) setting an adjustment value in dependence on the results of the comparisons; and adding, in an increment/decrement hardware unit, the adjustment value to the intermediate m-bit number to generate the output m-bit number.

2 . The method according to claim 1 , wherein the look-up logic hardware unit comprises an arrangement of AND and OR logic blocks and wherein comparing pre-determined subsets of the bits of the input n-bit number with pre-determined values in fixed-function circuitry comprises:
for each of a plurality of pre-determined subsets of the bits of the input n-bit number, using a plurality of AND logic blocks to compare the subset to a pre-defined bit sequence, and wherein setting an adjustment value in dependence on the results of the comparisons comprises: in response to identifying a match between a subset and its corresponding pre-defined bit sequence, setting the adjustment value to a value associated with the pre-defined bit sequence.

3 . A method of mapping an input n-bit number to an output m-bit number, where n and m are integers and n<m, the method comprising:
appending, in a replication hardware unit, (m−n) most significant bits of the input n-bit number to the input n-bit number to form an intermediate m-bit number; in a look-up logic hardware unit: (i) comparing pre-determined subsets of the bits of the input n-bit number with pre-determined values in fixed-function circuitry, and (ii) setting an adjustment value in dependence on the results of the comparisons; and adding, in an increment/decrement hardware unit, the adjustment value to the intermediate m-bit number to generate the output m-bit number.

4 . The method according to claim 3 , wherein if m>2n, appending (m−n) most significant bits of the input n-bit number to the input n-bit number to form an intermediate m-bit number comprises:
appending (k−1) repetitions of the input n-bit number to the input n-bit number followed by r most significant bits of the input n-bit number, where k=└(m/n)┘ and r=m mod n.

5 . The method according to claim 3 , wherein the look-up logic hardware unit comprises an arrangement of AND and OR logic blocks and wherein comparing pre-determined subsets of the bits of the input n-bit number with pre-determined values in fixed-function circuitry comprises:
for each of a plurality of pre-determined subsets of the bits of the input n-bit number, using a plurality of AND logic blocks to compare the subset to a pre-defined bit sequence, and wherein setting an adjustment value in dependence on the results of the comparisons comprises: in response to identifying a match between a subset and its corresponding pre-defined bit sequence, setting the adjustment value to a value associated with the pre-defined bit sequence.

6 . Hardware logic arranged to map an input n-bit number to an output m-bit number, where n and m are integers and n>m, the hardware logic comprising:
a truncation hardware unit arranged to truncate the input n-bit number from n-bits to m-bits to form an intermediate m-bit number; a look-up logic hardware unit arranged to (i) compare pre-determined subsets of the bits of the input n-bit number with pre-determined values in fixed-function circuitry, and (ii) set an adjustment value in dependence on the results of the comparisons; and an increment/decrement hardware unit arranged to add the adjustment value to the intermediate m-bit number to generate the output m-bit number.

7 . Hardware logic configured to perform the method of claim 1 , optionally wherein the hardware logic is embodied in hardware on an integrated circuit.

8 . Hardware logic configured to perform the method of claim 3 , optionally wherein the hardware logic is embodied in hardware on an integrated circuit.

9 . A data compression unit comprising the hardware logic according to claim 6 .

10 . A data compression unit comprising the hardware logic according to claim 7 .

11 . A data compression unit comprising the hardware logic according to claim 8 .

12 . A non-transitory computer readable storage medium having stored thereon computer executable code that when executed causes at least one process to perform the method as set forth in claim 1 .

13 . A non-transitory computer readable storage medium having stored thereon computer executable code that when executed causes at least one process to perform the method as set forth in claim 3 .

14 . A method of manufacturing, using an integrated circuit manufacturing system, hardware logic as claimed in claim 6 .

15 . An integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture hardware logic as claimed in claim 6 .

16 . A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture hardware logic as claimed in claim 6 .

17 . An integrated circuit manufacturing system configured to manufacture hardware logic as claimed in claim 6 .

18 . An integrated circuit manufacturing system comprising:
a non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that describes hardware logic as claimed in claim 6 ; a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the hardware logic; and an integrated circuit generation system configured to manufacture the hardware logic according to the circuit layout description.

Assignees

• Imagination Tech Ltd

Inventors

• Fenney Simon

Classifications

• H04N19/42 Primary

  characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation (H04N19/635 takes precedence) · CPC title

• H04N19/44

  Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder · CPC title

• H04N19/184

  the unit being bits, e.g. of the compressed video stream · CPC title

• H04N19/176

  the region being a block, e.g. a macroblock · CPC title

• H04N19/186

  the unit being a colour or a chrominance component · CPC title