Increased transistor source/drain contact area using sacrificial source/drain layer

Patent metadata

Field	Value
Publication number	US-2020006525-A1
Application number	US-201816023024-A
Country	US
Kind code	A1
Filing date	Jun 29, 2018
Priority date	Jun 29, 2018
Publication date	Jan 2, 2020
Grant date	—

Abstract

Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material, such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device.

First claim

What is claimed is:

1 . An integrated circuit including at least one transistor, the integrated circuit comprising:
a body including semiconductor material; a gate electrode at least above the body, the gate electrode including one or more metals; a gate dielectric between the gate electrode and the body, the gate dielectric including one or more dielectrics; a source region and a drain region, the body between the source and drain regions, the source and drain regions including semiconductor material; a first contact structure at least above and below the source region, the first contact structure including one or more metals; and a second contact structure at least above and below the drain region, the second contact structure including one or more metals.

2 . The integrated circuit of claim 1 , wherein the first contact structure is further on at least one side of the source region and the second contact structure is further on at least one side of the drain region.

3 . The integrated circuit of claim 1 , wherein the first contact structure wraps around at least a portion of the source region and the second contact structure wraps around at least a portion of the drain region.

4 . The integrated circuit of claim 1 , further comprising a substrate, wherein a portion of the first contact structure is between the substrate and the source region, and a portion of the second contact structure is between the substrate and the drain region.

5 . The integrated circuit of claim 4 , further comprising a layer between the first contact structure and the substrate, the layer also between the second contact structure and the substrate, the layer including compositionally different material relative to the source and drain regions.

6 . The integrated circuit of claim 5 , wherein the layer includes one or more dielectrics.

7 . The integrated circuit of claim 1 , wherein the first contact structure is between two portions of the source region, and the second contact structure is between two portions of the drain region.

8 . The integrated circuit of claim 1 , wherein the source region is between two structures, the two structures including one or more dielectrics, the drain region also between the two structures.

9 . The integrated circuit of claim 1 , wherein the one or more metals included in the first and second contact structures include one or more transition metals.

10 . The integrated circuit of claim 9 , wherein the one or more transition metals include one or more of tungsten, titanium, tantalum, copper, cobalt, gold, nickel, or ruthenium.

11 . The integrated circuit of claim 1 , wherein the body includes germanium or group III-V semiconductor material.

12 . The integrated circuit of claim 1 , wherein the body is a fin, the fin between two portions of the gate electrode.

13 . The integrated circuit of claim 12 , wherein the fin has a height of at least 20 nanometers between the two portions of the gate electrode.

14 . The integrated circuit of claim 1 , wherein the gate electrode wraps around the body.

15 . The integrated circuit of claim 14 , wherein the body is a nanowire or a nanoribbon.

16 . A computing system comprising the integrated circuit of claim 1 .

17 . An integrated circuit including at least one transistor, the integrated circuit comprising:
a substrate; a body above the substrate, the body including semiconductor material; a gate electrode at least above the body, the gate electrode including one or more metals; a gate dielectric between the gate electrode and the body, the gate dielectric including one or more dielectrics; a source region and a drain region, the body between the source and drain regions, the source and drain regions including semiconductor material; a first contact structure that wraps around the source region, a portion of the first contact structure between the substrate and the source region, the first contact structure including one or more metals; and a second contact structure that wraps around the drain region, a portion of the second contact structure between the substrate and the drain region, the second contact structure including one or more metals.

18 . The integrated circuit of claim 17 , wherein the body is a fin, a nanowire, or a nanoribbon.

19 . A method of forming an integrated circuit including at least one transistor, the method comprising:
providing a body including semiconductor material; forming a gate electrode at least above the body, the gate electrode including one or more metals; forming a gate dielectric between the gate electrode and the body, the gate dielectric including one or more dielectrics; forming a source region and a drain region, the body between the source and drain regions, the source and drain regions including semiconductor material; forming a first contact structure at least above and below the source region, the first contact structure including one or more metals; and forming a second contact structure at least above and below the drain region, the second contact structure including one or more metals.

20 . The method of claim 19 , further comprising:
forming a sacrificial layer in the source and drain regions; and removing the sacrificial layer prior to forming the first and second contact structures, such that a cavity is formed below each of the first and second contact structures to allow the first and second contact structures to be respectively formed below the source and drain regions.

Assignees

• Intel Corp

Inventors

• Crum Dax M
• Guha Biswajeet
• Hsu William
• Cea Stephen M
• Ghani Tahir

Classifications

• H10P14/3462

  Nanowires · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/785

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L29/66545 Primary

  Electricity · mapped topic