Package structure having substrate thermal vent structures for inductor cooling

Patent metadata

Field	Value
Publication number	US-2020006287-A1
Application number	US-201816025710-A
Country	US
Kind code	A1
Filing date	Jul 2, 2018
Priority date	Jul 2, 2018
Publication date	Jan 2, 2020
Grant date	—

Abstract

Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein the inductor is at least partially embedded within the substrate. One or more thermal vent structures extend through at least one of the substrate or a board attached to the substrate. The one or more thermal vent structures provide a thermal pathway for cooling for the inductor.

First claim

What is claimed is:

1 . An assembly comprising:
a substrate, the substrate comprising a first side and a second side opposite the first side; a die on the first side of the substrate, the die comprising an integrated circuit; an inductor, wherein the inductor is at least partially embedded within the substrate; a board electrically coupled to the second side of the substrate; and one or more openings extending through at least one of the substrate or the board, wherein the one or more openings are adjacent a sidewall of the inductor.

2 . The assembly of claim 1 , wherein one or more interconnect structures are on a second side of the substrate, adjacent a sidewall of an individual one of the one or more openings.

3 . The assembly of claim 2 , wherein a stand-off region is between the second side of the substrate and a first side of the board, wherein a portion of the standoff region beneath the inductor is free of the one or more interconnect structures, and wherein a first side of the inductor is embedded within the substrate, and a second side of the inductor is substantially coplanar with the second side of the substrate.

4 . The assembly of claim 1 , wherein an array of solder balls surrounds the die on a first portion of a peripheral region of the second side of the substrate, and wherein a second portion of the peripheral region of the second side of the substrate is free of the solder balls.

5 . The assembly of claim 4 , wherein an individual one of the one or more openings is between the array and the die.

6 . The assembly of claim 1 , wherein an air funnel is on the first side of the substrate, adjacent the die.

7 . The assembly of claim 1 , wherein a first side of the die is on the first side of the substrate, and wherein a heat sink is on a second side of the die, and wherein the heat sink has an opening adjacent the die.

8 . The assembly of claim 1 , wherein the die includes a portion of a voltage regulator, and wherein the inductor is electrically coupled to the voltage regulator.

9 . The assembly of claim 1 wherein the inductor comprises an air core inductor, wherein the air core inductor comprises one or more conductive layers coupled to each other by one or more conductive via structures.

10 . A microelectronic device package structure comprising:
a substrate; a die comprising an integrated circuit, wherein the die is on a first side of the substrate; an inductor, wherein the inductor is at least partially embedded within the substrate; and one or more openings extending through the substrate, wherein the one or more openings are adjacent a sidewall of the inductor.

11 . The microelectronic device package structure of claim 10 , further comprising a board electrically coupled to the second side of the substrate.

12 . The microelectronic device package structure of claim 11 , wherein the board comprises one or more openings through the board, wherein the one or more openings are adjacent the sidewall of the inductor.

13 . The microelectronic device package structure of claim 10 , wherein a heat sink is on the die and is thermally coupled to the die, wherein the heat sink comprises an opening extending through the heat sink, and wherein the opening through the heat sink is over an individual one of the one or more openings extending through the substrate.

14 . The microelectronic device package structure of claim 11 , wherein one or more interconnect structures are on a first side of the board, wherein the one or more interconnect structures are adjacent a sidewall of an individual one of the one or more openings in the board.

15 . The microelectronic device package structure of claim 10 , wherein the inductor comprises a portion of an air core inductor.

16 . The microelectronic device package structure of claim 10 wherein an air funnel is adjacent the die and on the first side of the substrate, and a fan is adjacent the air funnel.

17 . A method of fabricating a microelectronic package structure, comprising:
forming an inductor within a substrate, wherein the inductor is at least partially embedded within the substrate; and forming one or more openings through the substrate, wherein the one or more openings are adjacent a sidewall of the inductor.

18 . The method of fabricating the microelectronic package structure of claim 17 , wherein forming the inductor comprises forming a plurality of inductor layers within a recess of the substrate, wherein individual layers are coupled to each other by one or more via structures, and wherein a first side of the inductor is embedded within the substrate, and a portion of a second side of the inductor is substantially coplanar with a second side of the substrate.

19 . The method of fabricating the microelectronic package structure of claim 17 further comprising:
attaching a board on the substrate;
forming one or more board openings through the board, wherein the one or more board openings are adjacent to an inductor footprint.

20 . The method of fabricating the microelectronic package structure of claim 17 , further comprising attaching a die on a side of the substrate opposite the surface of the inductor.

Assignees

• Intel Corp

Inventors

• Hill Michael J
• Wojewoda Leigh E
• Manusharow Mathew
• Kulasekaran Siddharth

Classifications

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W40/00

  Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) · CPC title

• H10W70/681

  comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title