Dummy Dies for Reducing Warpage in Packages

Patent metadata

Field	Value
Publication number	US-2020006252-A1
Application number	US-201916273887-A
Country	US
Kind code	A1
Filing date	Feb 12, 2019
Priority date	Jul 2, 2018
Publication date	Jan 2, 2020
Grant date	—

Abstract

A method includes placing a plurality of functional dies over a carrier, placing a plurality of dummy dies over the carrier, encapsulating the plurality of functional dies and the plurality of dummy dies in an encapsulant, and forming redistribution lines over and interconnecting the plurality of functional dies. The redistribution lines, the plurality of functional dies, the plurality of dummy dies, and the encapsulant in combination form a reconstructed wafer. The plurality of functional dies are in a center region of the reconstructed wafer, and the plurality of dummy dies are in a peripheral region of the reconstructed wafer, with the peripheral region encircling the center region. The reconstructed wafer is de-bonded from the carrier. The reconstructed wafer is bonded to a package component selected from the group consisting essentially of an interposer, a package substrate, a printed circuit board, a thermal module, and combinations thereof.

First claim

What is claimed is:

1 . A method comprising:
placing a plurality of functional dies over a carrier; placing a plurality of dummy dies over the carrier; encapsulating the plurality of functional dies and the plurality of dummy dies in an encapsulant; forming redistribution lines over and interconnecting the plurality of functional dies, wherein the redistribution lines, the plurality of functional dies, the plurality of dummy dies, and the encapsulant in combination form a reconstructed wafer, wherein the plurality of functional dies are in a center region of the reconstructed wafer, and the plurality of dummy dies are in a peripheral region of the reconstructed wafer, with the peripheral region encircling the center region; de-bonding the reconstructed wafer from the carrier; and bonding the reconstructed wafer to a package component selected from the group consisting essentially of an interposer, a package substrate, a printed circuit board, a thermal module, and combinations thereof.

2 . The method of claim 1 , wherein the plurality of dummy dies are distributed substantially uniformly in the peripheral region.

3 . The method of claim 1 , wherein the reconstructed wafer bonded to the package component has a round top-view shape.

4 . The method of claim 1 , wherein the reconstructed wafer is un-sawed before being bonded to the package component.

5 . The method of claim 1 further comprising securing the reconstructed wafer to the package component through a bolt penetrating through the reconstructed wafer.

6 . The method of claim 5 , wherein the bolt penetrates through one of the plurality of dummy dies.

7 . The method of claim 1 , wherein the encapsulating comprises:
dispensing the encapsulant; and planarizing the encapsulant, wherein a dummy die in the plurality of dummy dies is polished in the planarizing.

8 . The method of claim 1 , wherein the plurality of dummy dies are thinner than the plurality of functional dies, and wherein the encapsulating comprises:
dispensing the encapsulant; and planarizing the encapsulant, wherein after the planarizing, a layer of the encapsulant covers the plurality of dummy dies.

9 . The method of claim 1 , wherein the plurality of functional dies are placed as a plurality of groups, with inner-group spacings between dies in a same group being smaller than inter-group spacings between neighboring ones of the plurality of groups.

10 . The method of claim 9 further comprising placing an additional plurality of dummy dies between the plurality of groups.

11 . The method of claim 9 , wherein dies in one of the plurality of groups comprise a computing die and an input-output die.

12 . The method of claim 1 , further comprising placing a plurality of input-output dies surrounding the plurality of functional dies.

13 . A method comprising:
placing a plurality of logic dies over a carrier; placing a plurality of Input-output (IO) dies over the carrier; placing a plurality of dummy dies over the carrier, wherein the plurality of dummy dies are distributed surrounding a region in which the plurality of logic dies and the plurality of IO dies are located; encapsulating the plurality of logic dies, the plurality of IO dies, and the plurality of dummy dies in an encapsulant; forming redistribution lines over and electrically coupling to the plurality of logic dies and the plurality of TO dies to form a reconstructed wafer, and the reconstructed wafer comprises the plurality of logic dies, the plurality of TO dies, the plurality of dummy dies, the encapsulant, and the redistribution lines; and de-bonding the reconstructed wafer from the carrier.

14 . The method of claim 13 further comprising, without sawing the reconstructed wafer, bonding the reconstructed wafer to a package component.

15 . The method of claim 13 further comprising, before the encapsulating, inserting a dummy die between two of the plurality of logic dies.

16 . The method of claim 13 , wherein the plurality of logic dies are placed as parts of a plurality of groups, with inner-group spacings between dies in a same group being smaller than inter-group spacings between neighboring ones of the plurality of groups.

17 . The method of claim 16 , wherein the plurality of TO dies are placed as parts of the plurality of groups.

18 . A package comprising:
a reconstructed wafer comprising:
a plurality of dummy dies;
a plurality of functional dies in a center region of the package, wherein the plurality of dummy dies are allocated aligning a ring encircling the plurality of functional dies;
an encapsulant encapsulating the plurality of dummy dies and the plurality of functional dies therein; and
a plurality of Redistribution Lines (RDLs) over the plurality of functional dies, wherein the plurality of RDLs interconnect all functional dies in the package into an integrated system.

19 . The package of claim 18 further comprising a package component bonded to the reconstructed wafer, wherein the package component is selected from the group consisting essentially of an interposer, a package substrate, a printed circuit board, a thermal module, and combinations thereof.

20 . The package of claim 19 , wherein the reconstructed wafer that is bonded to with the package component has a round top-view shape.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Kuo Tin-Hao
• Tsai Hao-Yi
• Liu Chung-Shi

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/9413

  on encapsulations · CPC title