Fully integrated voltage regulator circuitry within a substrate

Patent metadata

Field	Value
Publication number	US-2020006239-A1
Application number	US-201816024717-A
Country	US
Kind code	A1
Filing date	Jun 29, 2018
Priority date	Jun 29, 2018
Publication date	Jan 2, 2020
Grant date	—

Abstract

Embodiments herein relate to integrating FIVR switching circuitry into a substrate that has a first side and a second side opposite the first side, where the first side of the substrate to electrically couple with a die and to provide voltage to the die and the second side of the substrate is to couple with an input voltage source. In embodiments, the FIVR switching circuitry may be printed onto the substrate using OFET, CNT, or other transistor technology, or may be included in a separate die that is incorporated within the substrate.

First claim

What is claimed is:

1 . A package comprising:
a substrate, having a first side and a second side opposite the first side, the first side of the substrate to electrically couple with a die and to provide voltage to the die, and the second side of the substrate to couple with an input voltage source; and wherein the substrate is to include fully integrated voltage regulator (FIVR) circuitry to regulate a voltage to the die.

2 . The package of claim 1 , wherein at least a portion of the FIVR circuitry is included within another die included within the substrate and electrically coupled with the first side of the substrate and with the second side of the substrate.

3 . The package of claim 2 , wherein the other die has a first side and a second side opposite the first side, and wherein the first side of the other die is adjacent to a metal layer.

4 . The package of claim 2 , wherein the other die is disposed within a cavity in a layer of the substrate.

5 . The package of claim 1 , wherein at least a portion of the FIVR circuitry further includes one or more Organic Field Effect Transistors (OFET) within the substrate to provide FIVR switching circuitry.

6 . The package of claim 5 , wherein at least one of the one or more OFET has a thickness of approximately 1 micrometer.

7 . The package of claim 5 , wherein a copper (Cu) block is proximate to the OFET to serve as a heat sink for the OFET.

8 . The package of claim 1 , wherein at least a portion of the FIVR circuitry further includes one or more carbon nanotubes transistor (CNT) within the substrate to provide FIVR switching circuitry.

9 . The package of claim 1 , wherein at least a portion of the FIVR circuitry further includes one or more oxide thin-film transistors within the substrate to provide FIVR switching circuitry.

10 . The package of claim 1 , wherein one or more air core inductors or magnetic inductors are disposed between and are electrically coupled to the first side of the substrate and to the FIVR circuitry.

11 . A method for creating a fully integrated voltage regulator (FIVR) within a substrate using an embedded die, the method comprising:
embedding the die into a first side of the substrate, wherein the substrate includes a inductor having a first end electrically coupled to a second side of the substrate opposite the first side of the substrate, wherein a second end of the inductor opposite the first end is electrically coupled to the embedded die, wherein the embedded die includes circuitry to perform FIVR switching; and electrically coupling a connection on the substrate to the embedded die to allow the embedded die to receive a voltage external to the substrate.

12 . The method of claim 11 , wherein embedding the die into to the first side of the substrate further includes:
applying a metal layer to a portion of the first side of the substrate; applying a dielectric layer to cover at least a portion of the metal layer; removing a portion of the applied dielectric layer to form a cavity within the applied dielectric layer, wherein the metal layer is to provide an edge of the cavity; and inserting the die into the cavity.

13 . The method of claim 12 , wherein removing a portion of the applied dielectric layer further includes laser drilling or etching the applied dielectric layer.

14 . The method of claim 12 , wherein the dielectric layer is a buildup layer.

15 . The method of claim 11 , wherein the inductor is a first inductor; and further comprising a second inductor, wherein the first and the second inductors are substantially perpendicular to a plane of the substrate.

16 . A method for creating a fully integrated voltage regulator (FIVR) within a substrate, the method comprising:
coupling a transistor onto a first side of the substrate, wherein the substrate includes a magnetic inductor having a first end electrically coupled to a second side of the substrate opposite the first side of the substrate, wherein a second end of the inductor opposite the first end is electrically coupled to the transistor and wherein the transistor is to provide FIVR switching; and electrically coupling a connection on the substrate to the transistor to allow the transistor to receive a voltage external to the substrate.

17 . The method of claim 16 , wherein the inductor is a first inductor; and further comprising a second inductor, wherein the first and the second inductors are substantially perpendicular to a plane of the substrate.

18 . The method of claim 16 , wherein the transistor is an Organic Field Effect Transistor (OFET); and wherein coupling the OFET onto a first side of the substrate further includes coupling the OFET using lithography or using printing and laser sintering.

19 . The method of claim 16 , wherein the transistor is a carbon nanotube transistor (CNT); and
wherein applying the CNT onto a first side of the substrate further includes printing a nanoparticle solution onto the first side of the substrate.

20 . The method of claim 19 , further comprising sintering nanoparticles included in the nanoparticle solution using an ion laser beam to form conductor patterns.

Assignees

• Intel Corp

Inventors

• Zhang Chong
• Bharath Krishna

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title