Classification and localization of hotspots in integrated physical design layouts

Patent metadata

Field	Value
Publication number	US-2020004918-A1
Application number	US-201816020417-A
Country	US
Kind code	A1
Filing date	Jun 27, 2018
Priority date	Jun 27, 2018
Publication date	Jan 2, 2020
Grant date	—

Abstract

Methods and systems for fabricating an integrated circuit include training a machine learning model using a training set that includes known physical design layout patterns that are classified according to whether the patterns include a hotspot. It is determined whether an input physical design layout pattern includes a hotspot using the machine learning model. A hotspot localization is generated for the input physical design layout patterns. The input physical design pattern is adjusted to cure the hotspot. A circuit is fabricated in accordance with the adjusted input physical design layout pattern.

First claim

What is claimed is:

1 . A method for fabricating an integrated circuit, comprising:
training a machine learning model using a training set that includes known physical design layout patterns that are classified according to whether the patterns include a hotspot; determining whether an input physical design layout pattern includes a hotspot using the machine learning model; generating a hotspot localization for the input physical design layout patterns; adjusting the input physical design pattern to cure the hotspot; and fabricating a circuit in accordance with the adjusted input physical design layout pattern.

2 . The method of claim 1 , further comprising segmenting an input physical design layout into a plurality of input physical design layout patterns, wherein said determining, generating, and adjusting are repeated for each of the plurality of input physical design layout patterns before fabrication of the circuit.

3 . The method of claim 1 , wherein the input physical design layout pattern comprises a plurality of stacked layers.

4 . The method of claim 3 , wherein determining whether the input physical design layout patterns include a hotspot comprises considering all of the plurality of layers simultaneously to capture interlayer hotspots.

5 . The method of claim 1 , wherein the machine learning model comprises a convolutional neural network configured to determine whether the input physical design layout pattern includes one or more hotspots.

6 . The method of claim 1 , wherein generating a hotspot localization comprises generating a heat map overlay for the physical design layout pattern that shows regions with a higher likelihood of a hotspot as a higher heat map intensity.

7 . The method of claim 1 , wherein a hotspot represents an area of a physical design layout pattern that is not manufacturable or that render the circuit inoperable.

8 . The method of claim 1 , wherein adjusting the input physical design pattern comprises an action selected from the group consisting of moving circuit components and rerouting conductive paths.

9 . The method of claim 1 , further comprising verifying that the input physical design layout pattern includes a hotspot using a process simulation or fabrication on wafer after determining that the input physical design layout pattern includes a hotspot using the machine learning model.

10 . A non-transitory computer readable storage medium comprising a computer readable program for fabricating an integrated circuit, wherein the computer readable program when executed on a computer causes the computer to perform the steps of claim 1 .

11 . A method for fabricating an integrated circuit, comprising:
training a convolutional neural network using a training set that includes known multi-layer physical design layout patterns that are classified according to whether the patterns include a hotspot; determining whether an input multi-layer physical design layout pattern includes a hotspot using the convolutional neural network on all layers of the multi-layer circuit physical layout patterns simultaneously; verifying that the input physical design layout pattern includes a hotspot using a simulation after determining that the input physical design layout pattern includes a hotspot using the convolutional neural network; generating a hotspot heat map for the input multi-layer physical design layout pattern that shows regions with a higher likelihood of a hotspot as a higher heat map intensity; adjusting the input physical design pattern to cure the hotspot; and fabricating a circuit in accordance with the adjusted input multi-layer physical design layout pattern.

12 . A system for fabricating an integrated circuit, comprising:
a training module configured to train a machine learning model using a training set that includes known physical design layout patterns that are classified according to whether the patterns include a hotspot, wherein the machine learning model is configured to determine whether an input physical design layout pattern includes a hotspot using the machine learning model and to generate a hotspot localization for the input physical design layout pattern; a layout adjustment module configured to adjust the input physical design pattern to cure the hotspot; and a fabrication module configured to trigger fabrication of a circuit in accordance with the adjusted input physical design layout pattern.

13 . The system of claim 12 , further comprising a segmentation module configured to segment an input physical design layout into a plurality of input physical design layout patterns, wherein the determination of the hotspot, generation of hotspot localization, and adjustment of the input physical design pattern are repeated for each of the plurality of input physical design layout patterns before fabrication of the circuit.

14 . The system of claim 12 , wherein the input physical design layout pattern comprises a plurality of stacked layers.

15 . The system of claim 14 , wherein the machine learning model is further configured to consider all of the plurality of layers simultaneously to capture interlayer hotspots.

16 . The system of claim 12 , wherein the machine learning model comprises a convolutional neural network configured to determine whether the input physical design layout pattern includes one or more hotspots.

17 . The system of claim 12 , wherein the machine learning model is further configured to generate a heat map overlay for the layout pattern that shows regions with a higher likelihood of a hotspot as a higher heat map intensity.

18 . The system of claim 12 , wherein a hotspot represents an area of a physical design layout pattern that is not manufacturable or that render the circuit inoperable.

19 . The system of claim 12 , wherein the adjustment module is further configured to perform an action selected from the group consisting of moving circuit components and rerouting conductive paths.

20 . The system of claim 12 , further comprising a verification module configured to verify that the input physical design layout pattern includes a hotspot using a simulation after the determination that the input physical design layout pattern includes a hotspot.

Assignees

• IBM

Inventors

• Sha Jing
• Shao Dongbing
• Burkhardt Martin
• Guillorn Michael A

Classifications

• G03F7/70433

  Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors · CPC title

• G03F7/705

  Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions · CPC title

• G03F1/70

  Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title