Dual purpose boot registers
US-2017315818-A1 · Nov 2, 2017 · US
Information processing device, information processing method, and non-transitory computer readable medium
US2020004647A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2020004647-A1 |
| Application number | US-201816150963-A |
| Country | US |
| Kind code | A1 |
| Filing date | Oct 3, 2018 |
| Priority date | Jun 29, 2018 |
| Publication date | Jan 2, 2020 |
| Grant date | — |
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- Title
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Abstract
Official abstract text for this publication.
The present invention provides an information processing device comprising a memory; a non-volatile memory; and a processor coupled to the memory and the non-volatile memory, the processor configured to: store in the non-volatile memory a snapshot of the memory in a state where a part of an activation process is implemented; and implement the activation process by using the snapshot stored in the non-volatile memory. More specifically, store in the non-volatile memory a snapshot of the main memory in a state before feeding a program to the external memory in an activation process using the main memory and the external memory; and implement at least a process of feeding a program for an external memory to the external memory from the main memory.
First claim
Opening claim text (preview).
What is claimed is: 1 . An information processing device comprising: a memory; a non-volatile memory; and a processor coupled to the memory and the non-volatile memory, the processor configured to: store in the non-volatile memory a snapshot of the memory in a state where a part of an activation process is implemented; and implement the activation process by using the snapshot stored in the non-volatile memory. 2 . The information processing device according to claim 1 , wherein the processor is further configured to implement the remaining activation process after using the snapshot stored in the non-volatile memory. 3 . The information processing device according to claim 2 , wherein the processor is further configured to store in the non-volatile memory a snapshot of a state where an activation process using a main memory and an external memory is partly implemented. 4 . The information processing device according to claim 3 , wherein the processor is further configured to: store in the non-volatile memory a snapshot of the main memory in a state before feeding a program to the external memory in an activation process using the main memory and the external memory; and implement at least a process of feeding a program for an external memory to the external memory from the main memory. 5 . The information processing device according to claim 1 , wherein the processor is further configured to: generate a snapshot of the memory after a language setting of a non-transitory computer readable medium is performed; store the generated snapshot in the non-volatile memory; and implement an activation process remaining after the language setting is performed, based on the snapshot stored in the non-volatile memory. 6 . An information processing method comprising the steps of: generating a snapshot of a memory in a state where an activation process is partly implemented; and distributing the generated snapshot. 7 . A non-transitory computer-readable recording medium storing a program comprising: a snapshot of a memory in a state where an activation process is partly implemented.
Assignees
Inventors
Classifications
- G06F8/63Primary
Image based installation; Cloning; Build to order · CPC title
using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories · CPC title
Bootstrapping (security arrangements therefor G06F21/57) · CPC title
- G06F11/1471Primary
involving logging of persistent data for recovery · CPC title
to make the backup process non-disruptive · CPC title
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Frequently asked questions
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- What does patent US2020004647A1 cover?
- The present invention provides an information processing device comprising a memory; a non-volatile memory; and a processor coupled to the memory and the non-volatile memory, the processor configured to: store in the non-volatile memory a snapshot of the memory in a state where a part of an activation process is implemented; and implement the activation process by using the snapshot stored in t…
- Who is the assignee on this patent?
- Pfu Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F8/63. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu Jan 02 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).