Card and host apparatus

Patent metadata

Field	Value
Publication number	US-2020004318-A1
Application number	US-201916564441-A
Country	US
Kind code	A1
Filing date	Sep 9, 2019
Priority date	Dec 27, 2004
Publication date	Jan 2, 2020
Grant date	—

Abstract

A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.

First claim

1 - 10 . (canceled)

11 : A memory system comprising a host apparatus connectable to a memory device which comprises a memory core and a memory controller, the host apparatus configured to:
send a first command to the memory device, receive a response transmitted from the memory device, in response to the first command, the response including status data that is used to determine whether the memory device supports a termination process, the termination process including shifting into a state ready for a stop of power supply from the host apparatus, send a function stop command to the memory device so that the memory device performs the termination process in response to the function stop command, receive a first signal while performing the termination process, the first signal being indicative of a busy state and having a first level, and receive as a notification a second signal being indicative of a ready state and having a second level when the memory device completes the termination process.

12 : The memory system according to claim 11 , wherein the termination process includes writing data stored in a volatile semiconductor memory into the memory core.

13 : The memory system according to claim 11 , wherein the memory system is configured to change the information to indicate that the termination process has not been completed when a status of the memory system has changed since completion of a latest initialization.

14 : The memory system according to claim 11 , wherein the memory system is configured to:
receive an initialization command instructing to carry out initialization, execute initialization using a first initialization method when the information indicates that the termination process has not been completed, and execute initialization using a second initialization method, which is finished quicker than the first initialization method, when the memory core indicates that the termination process has been completed.

15 : The memory system according to claim 14 , wherein the second initialization method comprises the first initialization method with a part of it omitted.

16 : The memory system according to claim 15 , wherein the omitted part includes at least one of checking for errors of data stored in the memory core, restoring the errors, and constructing a translation table showing a relation between logical addresses of write data and physical addresses of the memory core which stores the write data.

Assignees

• Toshiba Memory Corp

Inventors

• Fujimoto Akihisa

Classifications

• G06F13/4081

  Live connection to bus, e.g. hot-plugging (current or voltage limitation during live insertion H02H9/004) · CPC title

• G06F3/0632

  by initialisation or re-initialisation of storage systems · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F1/3281

  Power saving in PCMCIA card · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title