Communication unit, integrated circuits and method for clock and data synchronization

Patent metadata

Field	Value
Publication number	US-2020003883-A1
Application number	US-201916447962-A
Country	US
Kind code	A1
Filing date	Jun 21, 2019
Priority date	Jul 2, 2018
Publication date	Jan 2, 2020
Grant date	—

Abstract

A communication unit ( 700 ) is described that includes a plurality of cascaded devices that comprise at least one master device ( 710 ) and at least one slave device ( 720, 723 ) configured in a master-slave arrangement. The at least one master device ( 710 ) and at least one slave device ( 720, 723 ) each comprise: an analog-to-digital converter, ADC, ( 741, 742 ) configured to use a same re-created system clock signal ( 788, 790 ) to align respective sampling instants between each ADC ( 741, 742 ). The at least one master device ( 710 ) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit ( 708 ), configured to output a system clock signal ( 782, 784 ); and a modulator circuit ( 762 ) coupled to the clock generation circuit and configured to receive and distribute the system clock signal ( 784 ). The at least one master device ( 710 ) and at least one slave device ( 720, 723 ) each comprise: a demodulator circuit ( 764, 765 ) configured to receive the distributed system clock signal ( 784 ) and re-create therefrom a synchronized system clock signal ( 788, 790 ) used by a respective ADC, ( 741, 742 ) of each of the the master device ( 710 ) and at least one slave device ( 720 ).

First claim

1 . A communication unit comprising:
a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement; wherein the at least one master device and at least one slave device each comprise: an analog-to-digital converter, ADC, configured to use a same re-created system clock signal to align respective sampling instants between each ADC
wherein the communication unit is characterized in that:
the at least one master device comprises:
a clock generation circuit comprising an internally-generated reference phase locked loop circuit configured to output a system clock signal; and
a modulator circuit coupled to the clock generation circuit and configured to receive and distribute the system clock signal;

wherein the at least one master device and at least one slave device each comprise:
a demodulator circuit configured to receive the distributed system clock signal and re-create therefrom a synchronized system clock signal used by a respective ADC, of each of the the master device and at least one slave device.

2 . The communication unit of claim 1 wherein the ADCs of each of the at least one master device and at least one slave device is configured to use the same re-created system clock signal such that respective sampling instants between each ADC are time-aligned.

3 . The communication unit of of claim 1 , wherein at least one of the at least one master device and at least one slave device further comprises:
a digital controller coupled to the demodulator circuit and configured to re-sample the re-created synchronized system clock signal.

4 . The communication unit of claim 1 , wherein the modulator circuit is configured to receive a system clock signal and a frame start signal and embed the frame start signal into the system clock signal and distribute a modulated embedded master-slave system clock signal.

5 . The communication unit of claim 4 wherein at least one of the at least one master device and at least one slave device comprises:
a demodulator circuit configured to receive and demodulate the modulated embedded master-slave clock signal and re-create therefrom a system clock signal and a frame start signal.

6 . The communication unit of claim 4 , wherein the communication unit is a radar unit and the frame start signal is a chirp start signal.

7 . The communication unit of claim 1 , wherein the clock generation circuit of the at least one master device comprises a XOR-based phase locked loop.

8 . The communication unit of claim 1 , wherein the at least one master device and at least one slave device are configured to use low-voltage differential signalling, LVDS, to assist modulation and demodulation of the clock signal.

9 . The communication unit of claim 1 , wherein at least one of: the modulator circuit and demodulator circuit is terminated by a differential resistor.

10 . An integrated circuit for a master device in a master-slave arrangement, wherein the integrated circuit comprises an analog-to-digital converter, ADC, configured to use a same re-created system clock signal to align respective sampling instants between each ADC across multiple devices;
wherein the integrated circuit is characterized by:
a clock generation circuit comprising an internally-generated reference phase locked loop circuit, configured to output a system clock signal;
a modulator circuit coupled to the clock generation circuit and configured to receive and distribute the system clock signal to at least two of the master device and at least one slave device; and
a demodulator circuit configured to receive the distributed system clock signal and re-create therefrom a synchronized system clock signal used by a respective ADC, of each of the the master device and at least one slave device.

11 . A method for clock distribution and synchronization in a communication unit having at least one master device and at least one slave device configured in a master-slave arrangement, wherein the method comprises, at a master device:
generating internally to the master device a system clock signal; wherein the method is characterized by: distributing the system clock signal to at least two of the master device and at least one slave device; receiving the distributed system clock signal; and
re-creating therefrom a synchronized system clock signal used by a respective ADC, of each of the the master device and at least one slave device.

Assignees

• Nxp Usa Inc

Inventors

• Doaré Olivier
• Salle Didier
• Pavao Moreira Cristian
• Orlando Julien
• Vigier Jean-Stephane
• Barrilado Gonzalez Andres

Classifications

• G01S7/36

  Means for anti-jamming {, e.g. ECCM, i.e. electronic counter-counter measures} · CPC title

• G01S7/02 Primary

  of systems according to group G01S13/00 · CPC title

• H04J3/0685

  Clock or time synchronisation in a node; Intranode synchronisation · CPC title

• G01S13/931

  of land vehicles · CPC title

• G01S13/88

  Radar or analogous systems specially adapted for specific applications (electromagnetic prospecting or detecting of objects, e.g. near-field detection, G01V3/00) · CPC title