Secure boot with resistance to differential power analysis and other external monitoring attacks

Patent metadata

Field	Value
Publication number	US-2019377879-A1
Application number	US-201916240671-A
Country	US
Kind code	A1
Filing date	Jan 4, 2019
Priority date	Dec 4, 2009
Publication date	Dec 12, 2019
Grant date	—

Abstract

A computing device includes a secure storage hardware to store a secret value and processing hardware comprising at least one of a cache or a memory. During a secure boot process the processing hardware loads untrusted data into at least one of the cache or the memory of the processing hardware, the untrusted data comprising an encrypted data segment and a validator, retrieves the secret value from the secure storage hardware, derives an initial key based at least in part on an identifier associated with the encrypted data segment and the secret value, verifies, using the validator, whether the encrypted data segment has been modified, and decrypts the encrypted data segment using a first decryption key derived from the initial key to produce a decrypted data segment responsive to verifying that the encrypted data segment has not been modified.

First claim

What is claimed is:

1 . A computing device comprising:
secure storage hardware to store a secret value; and processing hardware coupled to the secure storage hardware, the processing hardware comprising at least one of a cache or a memory, wherein during a secure boot process the processing hardware is to:
load untrusted data into at least one of the cache or the memory of the processing hardware, the untrusted data comprising an encrypted data segment and a validator;
retrieve the secret value from the secure storage hardware;
derive an initial key based at least in part on an identifier associated with the encrypted data segment and the secret value;
verify, using the validator, whether the encrypted data segment has been modified; and
decrypt the encrypted data segment using a first decryption key derived from the initial key to produce a decrypted data segment responsive to verifying that the encrypted data segment has not been modified.

Assignees

• Cryptography Res Inc

Inventors

• Kocher Paul C
• Rohatgi Pankaj
• Jaffe Joshua M

Classifications

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F21/575 Primary

  Secure boot · CPC title

• H04L9/0631

  Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms · CPC title

• H04L2463/061

  applying further key derivation, e.g. deriving traffic keys from a pair-wise master key · CPC title

• H04L9/0894

  Escrow, recovery or storing of secret information, e.g. secret key escrow or cryptographic key storage · CPC title