Increased source and drain contact edge width in two-dimensional material field effect transistors by directed self-assembly

Patent metadata

Field	Value
Publication number	US-2019371925-A1
Application number	US-201815991023-A
Country	US
Kind code	A1
Filing date	May 29, 2018
Priority date	May 29, 2018
Publication date	Dec 5, 2019
Grant date	—

Abstract

The present invention provides a method and a structure of increasing source and drain contact edge width in a two-dimensional material field effect transistor. The method includes patterning a two-dimensional material over an insulating substrate; depositing a gate dielectric over the two-dimensional material; depositing a top gate over the gate dielectric, wherein the top gate has a hard mask thereon; forming a sidewall spacer around the top gate; depositing an interlayer dielectric oxide over the sidewall spacer and the hard mask; removing the interlayer dielectric oxide adjacent to the sidewall spacer to form an open contact trench; depositing a copolymer coating in the contact trench region; annealing the copolymer to induce a directed self-assembly; performing a two-dimensional material etch over the two-dimensional material; removing the unetched copolymer without etching the gate dielectric; and etching the exposed gate in the source and the drain region to form a metal contact layer.

First claim

1 . A method of increasing a source region and a drain region contact edge width in a two-dimensional material field effect transistor, the method comprising:
patterning a two-dimensional material over an insulating substrate to define a channel width; depositing a gate dielectric over and in contact with the two-dimensional material; depositing a top gate over the gate dielectric, wherein the top gate has a hard mask thereon; forming a sidewall spacer around the top gate and the hard mask thereon; depositing an interlayer dielectric oxide over the sidewall spacer and the hard mask; removing the interlayer dielectric oxide adjacent to the sidewall spacer to form an open contact trench; depositing a cylinder-forming block copolymer coating in the contact trench region over the gate dielectric; annealing the cylinder-forming block copolymer to induce a directed self-assembly; etching over the cylinder-forming block copolymer coating to form a template; etching the gate dielectric using the template to expose the two-dimensional material underneath; performing a two-dimensional material etch over the two-dimensional material; selectively removing the unetched cylinder-forming block copolymer without etching the gate dielectric; and etching the exposed gate in the source region and the drain region to form a metal contact layer over the two-dimensional material.

2 . The method of increasing the source region and the drain region contact edge width in the two-dimensional material field effect transistor of claim 1 , wherein chemical metal polishing is performed on top of the hard mask.

3 . The method of increasing the source region and the drain region contact edge width in the two-dimensional material field effect transistor of claim 1 , wherein the deposition of the gate dielectric can be achieved through atomic layer deposition.

4 . The method of increasing the source region and the drain region contact edge width in the two-dimensional material field effect transistor of claim 1 , wherein the deposition of the gate dielectric can be achieved through chemical vapor deposition.

5 . The method of increasing the source region and the drain region contact edge width in the two-dimensional material field effect transistor of claim 1 , wherein the deposition of the gate dielectric can be achieved through plasma deposition.

6 . The method of increasing the source region and the drain region contact edge width in the two-dimensional material field effect transistor of claim 1 , wherein the deposition of the gate dielectric can be achieved through spin coating.

7 . A two-dimensional material field effect transistor comprising:
a two-dimensional material disposed on an insulating substrate; a recessed gate dielectric disposed on the two-dimensional material; a top gate disposed on the recessed gate dielectric; a hard mask disposed on the top gate; an interlayer dielectric oxide disposed on the hard mask; a set of sidewall spacers, wherein each of the set of sidewall spacers is disposed on opposing sides of the recessed gate dielectric, the top gate, and the hard mask wherein the set of sidewall spacers fails to be disposed along each side of the interlayer dielectric oxide; a gate metal contact layer disposed on the two-dimensional material and disposed directly on each side of the set of sidewall spacers and on each side of the interlayer dielectric oxide, and wherein a width of the interlayer dielectric oxide is greater than a width of the recessed gate dielectric.

8 . The two-dimensional material field effect transistor of claim 7 , wherein the gate metal contact layer is electrically insulated from the insulating substrate by a thin layer insulating material.

9 . The two-dimensional material field effect transistor of claim 7 , wherein the two-dimensional material is graphene.

10 . The two-dimensional material field effect transistor of claim 7 , wherein the two-dimensional material is hexagonal boron nitride.

12 . The two-dimensional material field effect transistor of claim 7 , wherein at least one of the set of sidewall spacers is silicon nitride.

13 . The two-dimensional material field effect transistor of claim 7 , wherein the top gate is amorphous silicon.

14 . The two-dimensional material field effect transistor of claim 7 , wherein at least one of the set of sidewall spacers has a lateral width from about 4 nanometers (nm) to about 30 nm and ranges between about 4 nm and about 30 nm.

15 . The two-dimensional material field effect transistor of claim 7 , wherein the insulating substrate has a lateral width from about 5 nanometers (nm) to about 100 nm and ranges between about 5 nm and about 100 nm.

16 . A method of increasing a source region and a drain region contact edge width in a two-dimensional material field effect transistor, the method comprising:
patterning a two-dimensional material over an insulating substrate to define a channel width; depositing a gate dielectric over and in contact with the two-dimensional material; depositing a top gate over the gate dielectric, wherein the top gate has a hard mask thereon; forming a sidewall spacer around the top gate and the hard mask thereon; depositing an interlayer dielectric oxide over the top gate and the hard mask thereon; removing the interlayer dielectric oxide adjacent to the top gate, the hard mask thereon, the source region, and the drain region; depositing a lamella-forming block copolymer coating into the trench region in the interlayer dielectric oxide; annealing the lamella-forming block copolymer to induce a directed self-assembly; etching over the lamella-forming block copolymer coating; etching over the gate dielectric to expose the two-dimensional material; performing a two-dimensional material etch over the two-dimensional material; selectively removing the unetched lamella-forming block copolymer materials without etching gate dielectric and interlayer dielectric oxide; and etching the exposed gate dielectric in the source region and the drain region to form a gate metal contact layer over the two-dimensional material.

17 . The method of increasing the source region and the drain region contact edge width in the two-dimensional material field effect transistor of claim 16 , wherein performing a polymethylmethacrylate etch over the copolymer coating leaves a mesh template.

18 . The method of increasing the source region and the drain region contact edge width in the two-dimensional material field effect transistor of claim 16 , wherein the mesh template is made of polystyrene.

19 . The method of increasing the source and the drain region contact edge width in the two-dimensional material field effect transistor of claim 16 , wherein a polymethylmethacrylate (PMMA) etch is performed over the lamella-forming block copolymer coating.

20 . The method of increasing the source and the drain region contact edge width in the two-dimensional material field effect transistor of claim 16 , wherein lithography is performed in removing the interlayer dielectric oxide adjacent to the top gate, the hard mask thereon, the source region, and the drain region.

Assignees

• IBM

Inventors

• Liu Chi-Chun
• Yeung Chun Wing
• Zhang Chen

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H10P14/683

  carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title