Electronic Devices Having Low Refresh Rate Display Pixels With Reduced Sensitivity to Oxide Transistor Threshold Voltage

Patent metadata

Field	Value
Publication number	US-2019371237-A1
Application number	US-201916255691-A
Country	US
Kind code	A1
Filing date	Jan 23, 2019
Priority date	Jun 5, 2018
Publication date	Dec 5, 2019
Grant date	—

Abstract

A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may include a drive transistor coupled in series with one or more emission transistors and a respective organic light-emitting diode (OLED). A semiconducting-oxide transistor may be coupled between a drain terminal and a gate terminal of the drive transistor to help reduce leakage during low-refresh-rate display operations. A silicon transistor may be further interposed between the semiconducting-oxide transistor and the gate terminal of the drive transistor. One or more capacitor structures may be coupled to the source terminal and/or the drain terminal of the semiconducting-oxide transistor to reduce rebalancing current that might flow through the semiconducting-oxide transistor as it is turned off. Configured in this way, any emission current flowing through the OLED will be insensitive to any potential drift in the threshold voltage of the semiconducting-oxide transistor.

First claim

1 . A display pixel, comprising:
a light-emitting diode; a drive transistor coupled in series with the light-emitting diode, wherein the drive transistor comprises a drain terminal, a gate terminal, and a source terminal; a transistor of a first semiconductor type coupled between the drain terminal and the gate terminal of the drive transistor, wherein the transistor of the first semiconductor type is configured to reduce leakage at the gate terminal of the drive transistor, and wherein the transistor of the first semiconductor type has a threshold voltage; and a transistor of a second semiconductor type different than the first semiconductor type, wherein the transistor of the second semiconductor type is interposed between the transistor of the first semiconductor type and the gate terminal of the drive transistor, and wherein the transistor of the second semiconductor type is configured to reduce the sensitivity of an emission current that flows through the light-emitting diode to the threshold voltage of the transistor of the first semiconductor type.

2 . The display pixel of claim 1 , wherein the transistor of the first semiconductor type comprises a semiconducting-oxide thin-film transistor having a channel formed in semiconducting-oxide.

3 . The display pixel of claim 2 , wherein the transistor of the second semiconductor type comprises a silicon thin-film transistor having a channel formed in silicon.

4 . The display pixel of claim 3 , wherein the transistor of the first semiconductor type and the transistor of the second semiconductor type are both n-channel thin-film transistors.

5 . The display pixel of claim 3 , wherein the transistor of the first semiconductor type is an n-channel thin-film transistor, and wherein the transistor of the second semiconductor type is a p-channel thin-film transistor.

6 . The display pixel of claim 3 , further comprising:
a storage capacitor coupled to the gate terminal of the drive transistor, wherein the storage capacitor is configured to store a data signal for the display pixel; and a matching capacitor coupled to an intermediate node between the transistor of the first semiconductor type and the transistor of the second semiconductor type, wherein the matching capacitor is configured to reduce a rebalancing current that flows through the transistor of the first semiconductor type as the transistor of the first semiconductor type is turned off.

7 . The display pixel of claim 6 , wherein the matching capacitor is smaller than the storage capacitor.

8 . The display pixel of claim 3 , further comprising:
a storage capacitor coupled to the gate terminal of the drive transistor, wherein the storage capacitor is configured to store a data signal for the display pixel; and a matching capacitor coupled to the drain terminal of the drive transistor, wherein the matching capacitor is configured to reduce a rebalancing current that flows through the transistor of the first semiconductor type as the transistor of the first semiconductor type is turned off.

9 . The display pixel of claim 3 , wherein the transistor of the first semiconductor type has a gate terminal configured to receive a scan control signal, and wherein the transistor of the second semiconductor type has a gate terminal configured to receive an emission control signal that is different than the scan control signal.

10 . The display pixel of claim 3 , wherein the transistor of the first semiconductor type and the transistor of the second semiconductor type have gate terminals configured to receive the same scan control signal.

11 . The display pixel of claim 10 , wherein the transistor of the first semiconductor type has a first threshold voltage, and wherein the transistor of the second semiconductor type has a second threshold voltage that is greater than the first threshold voltage.

12 . The display pixel of claim 3 , further comprising:
a first emission transistor coupled in series with the drive transistor and the light-emitting diode; a second emission transistor coupled in series with the drive transistor and the light-emitting diode; an initialization transistor coupled directly to the light-emitting diode; and a data loading transistor coupled directly to the source terminal of the drive transistor.

13 . A method of operating a display pixel, comprising:
during an emission phase, using a drive transistor in the display pixel to convey an emission current to a light-emitting diode in the display pixel, wherein the drive transistor comprises a drain terminal and a gate terminal; using a transistor of a first semiconductor type coupled between the drain terminal and the gate terminal of the drive transistor to reduce leakage at the gate terminal of the drive transistor during the emission phase, wherein the transistor of the first semiconductor type has a threshold voltage; and using a transistor of a second semiconductor type interposed between the transistor of the first semiconductor type and the gate terminal of the drive transistor to reduce the sensitivity of the emission current to the threshold voltage of the transistor of the first semiconductor type.

14 . The method of claim 13 , wherein the transistor of the first semiconductor type comprises a semiconducting-oxide thin-film transistor, and wherein the transistor of the second semiconductor type comprises a silicon thin-film transistor.

15 . The method of claim 14 , further comprising:
providing a scan control signal to a gate terminal of the transistor of the first semiconductor type; providing an emission control signal that is different than the scan control signal to a gate terminal of the transistor of the second semiconductor type; and deasserting the emission control signal before a falling edge of the scan control signal and asserting the emission control signal after the falling edge of the scan control signal.

16 . The method of claim 14 , further comprising:
providing a scan control signal to a gate terminal of the transistor of the first semiconductor type; providing the scan control signal to a gate terminal of the transistor of the second semiconductor type; and turning off the transistor of the second semiconductor type before turning off the transistor of the first semiconductor type at a falling edge of the scan control signal.

17 . An electronic device, comprising:
a display having an array of display pixels, wherein each display pixel in the array of display pixels comprises:
a light-emitting diode;
a drive transistor coupled in series with the light-emitting diode, wherein the drive transistor comprises a drain terminal, a gate terminal, and a source terminal;
a semiconducting-oxide transistor coupled between the drain terminal and the gate terminal of the drive transistor; and
a silicon transistor coupled between the semiconducting-oxide transistor and the gate terminal of the drive transistor.

18 . The electronic device of claim 17 , wherein each display pixel in the array of display pixels further comprises:
a storage capacitor directly coupled to the gate terminal of the drive transistor; and a matching capacitor directly coupled to the semiconducting-oxide transistor, wherein the matching capacitor is configured to reduce a rebalancing current that flows through the semiconducting-oxide transistor.

19 . The electronic device of claim 18 , wherein the matching capacitor is substantially smaller than the storage capacitor.

20 . The electronic device of claim 19 , wher

Assignees

• Apple Inc

Inventors

• Qian Chuang
• Tsai Tsung-Ting
• Hsieh Cheng-Chih
• Yang Shyuan
• Chang Ting-Kuo
• Jamshidi Roudbari Abbas
• Chang Shih Chang

Classifications

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2320/0242

  Compensation of deficiencies in the appearance of colours · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title