Searchable Storage

Patent metadata

Field	Value
Publication number	US-2019370465-A1
Application number	US-201916543554-A
Country	US
Kind code	A1
Filing date	Aug 17, 2019
Priority date	Mar 7, 2016
Publication date	Dec 5, 2019
Grant date	—

Abstract

To achieve a better overall performance, a preferred pattern processor based on 3-D memory offsets large latency with massive parallelism. A searchable storage comprises a plurality of searchable 3-D memory dice, each of which has in-situ searching capabilities.

First claim

1 - 20 . (canceled)

21 . A searchable storage comprising a plurality of searchable 3-D memory dice, each of said searchable 3-D memory dice comprising: a single semiconductor substrate; an input bus for transferring at least a search pattern; a plurality of storage-processing units (SPU's) communicatively coupled with said input bus, wherein each of said SPU's comprises:
at least a 3-D non-volatile memory (3D-NVM) array including memory cells above said semiconductor substrate and storing at least a portion of data; a pattern-processing circuit on said semiconductor substrate for performing pattern processing for said search pattern and said portion of data; a plurality of intra-die connections for communicatively coupling said 3D-NVM array and said pattern-processing circuit; whereby the primary purpose of said searchable storage is long-term storage and the secondary purpose of said searchable storage is in-situ search.

22 . The searchable storage according to claim 21 , wherein said semiconductor substrate comprises at least a single-crystalline semiconductor material; and, said memory cells do not comprise any single-crystalline semiconductor material.

23 . The searchable storage according to claim 21 , wherein said plurality of SPU's include more than one thousand SPU's; or, said intra-die connections include contact vias through no semiconductor substrate.

24 . The searchable storage according to claim 21 , wherein said 3D-NVM array is a vertical 3D-NVM or a horizontal 3D-NVM.

25 . The searchable storage according to claim 21 being an anti-virus storage, wherein
said input bus transfers at least a portion of a virus pattern;
said 3D-NVM array stores at least a portion of data;
said pattern-processing circuit is a code-matching circuit for searching said virus pattern in said portion of data.

26 . The searchable storage according to claim 21 being a searchable big-data storage, wherein
said input bus transfers at least a portion of a keyword;
said 3D-NVM array stores at least a portion of data;
said pattern-processing circuit is a string-matching circuit for searching said keyword in said portion of data.

27 . The searchable storage according to claim 21 being a searchable audio storage, wherein
said input bus transfers at least a portion of an acoustic/language model;
said 3D-NVM array stores at least a portion of audio data;
said pattern-processing circuit is a speech-recognition circuit for performing speech recognition on said portion of audio data with said acoustic/language model.

28 . The searchable storage according to claim 21 being a searchable image storage, wherein
said input bus transfers at least a portion of an image model;
said 3D-NVM array stores at least a portion of image data;
said pattern-processing circuit is an image-recognition circuit for performing image recognition on said portion of image data with said image model.

29 . The searchable storage according to claim 21 , wherein full pattern processing on at least a fraction of said portion of data is performed by a standalone processor separate from said searchable storage.

30 . A pattern processor die, comprising a semiconductor substrate; an input bus for transferring at least a first portion of a first pattern; a plurality of storage-processing units (SPU's) communicatively coupled with said input bus, each of said SPU's comprising:
at least a 3-D non-volatile memory (3D-NVM) array including memory cells above said semiconductor substrate and storing at least a second portion of a second pattern; a pattern-processing circuit on said semiconductor substrate for performing pattern processing for said first and second patterns; a plurality of intra-die connections for communicatively coupling said 3D-NVM array and said pattern-processing circuit; wherein said semiconductor substrate comprises at least a single-crystalline semiconductor material; and, said memory cells do not comprise any single-crystalline semiconductor material.

31 . The pattern processor die according to claim 30 , wherein: said plurality of SPU's include more than one thousand SPU's; or, said intra-die connections include contact vias through no semiconductor substrate.

32 . The pattern processor die according to claim 30 , wherein said 3D-NVM array is a vertical 3D-NVM or a horizontal 3D-NVM.

33 . The pattern processor die according to claim 30 , wherein
said input bus transfers at least a portion of a network packet or a digital file; said 3D-NVM array stores at least a portion of a virus pattern; said pattern-processing circuit is a code-matching circuit for searching said virus pattern in said portion of said network packet or said digital file.

34 . The pattern processor die according to claim 30 , wherein
said input bus transfers at least a portion of data; said 3D-NVM array stores at least a portion of a keyword; said pattern-processing circuit is a string-matching circuit for searching said keyword in said portion of data.

35 . The pattern processor die according to claim 30 , wherein
said input bus transfers at least a portion of audio data; said 3D-NVM array stores at least a portion of an acoustic/language model; said pattern-processing circuit is a speech-recognition circuit for performing speech recognition on said portion of audio data with said acoustic/language model.

36 . The pattern processor die according to claim 30 , wherein
said input bus transfers at least a portion of image data; said 3D-NVM array stores at least a portion of an image model; said pattern-processing circuit is an image-recognition circuit for performing image recognition on said portion of image data with said image model.

37 . The pattern processor die according to claim 30 , wherein
said input bus transfers at least a portion of a virus pattern; said 3D-NVM array stores at least a portion of data; said pattern-processing circuit is a code-matching circuit for searching said virus pattern in said portion of data.

38 . The pattern processor die according to claim 30 , wherein
said input bus transfers at least a portion of a keyword; said 3D-NVM array stores at least a portion of data; said pattern-processing circuit is a string-matching circuit for searching said keyword in said portion of data.

39 . The pattern processor die according to claim 30 , wherein
said input bus transfers at least a portion of an acoustic/language model; said 3D-NVM array stores at least a portion of audio data; said pattern-processing circuit is a speech-recognition circuit for performing speech recognition on said portion of audio data with said acoustic/language model.

40 . The pattern processor die according to claim 30 , wherein
said input bus transfers at least a portion of an image model; said 3D-NVM array stores at least a portion of image data; said pattern-processing circuit is an image-recognition circuit for performing image recognition on said portion of image data with said image model.

Assignees

• Zhang Guobiao

Inventors

• Zhang Guobiao

Classifications

• G06F21/564 Primary

  by virus signature recognition · CPC title

• G06F13/4027 Primary

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06V10/75

  Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video features; Coarse-fine approaches, e.g. multi-scale approaches; using context analysis; Selection of dictionaries · CPC title

• G06F18/22

  Matching criteria, e.g. proximity measures · CPC title

• G06F2221/034

  Test or assess a computer or a system · CPC title