Array substrate, method for fabricating the same, display panel, and display device

Patent metadata

Field	Value
Publication number	US-2019355759-A1
Application number	US-201716065224-A
Country	US
Kind code	A1
Filing date	Dec 11, 2017
Priority date	Jun 8, 2017
Publication date	Nov 21, 2019
Grant date	—

Abstract

The present disclosure relates to an array substrate, a method for fabricating the same, a display panel, and a display device. The array substrate includes an active layer on a substrate, the active layer including a channel region, source/drain regions and a lightly doped drain region, a gate electrode and a first electrode on the active layer, and a gate electrode and the first electrode a first insulating layer, a barrier and a second electrode on the first insulating layer. A projection of the second electrode on the substrate at least partially overlaps that of the first electrode. A projection of the barrier on the substrate covers that of the lightly doped drain region on the substrate. The projection of the barrier on the substrate does not overlap that of the source/drain regions. The barrier and the second electrode are in the same layer.

First claim

1 . An array substrate comprising:
an active layer positioned on a substrate, the active layer comprising a channel region, source/drain regions positioned on both sides of the channel region, and a lightly doped drain region between the channel region and the source/drain regions; a gate electrode and a first electrode positioned on the active layer, a first insulating layer positioned on the gate electrode and the first electrode; and a barrier and a second electrode positioned on the first insulating layer, wherein a projection of the second electrode on the substrate at least partially overlaps a projection of the first electrode on the substrate, wherein a projection of the barrier on the substrate covers a projection of the lightly doped drain region on the substrate, wherein the projection of the barrier on the substrate does not overlap projections of the source/drain regions on the substrate, and wherein the barrier and the second electrode are disposed in the same layer.

2 . The array substrate according to claim 1 , wherein the barrier has an opening, and wherein a projection of the opening on the substrate at least partially overlaps the projection of the gate electrode on the substrate.

3 . The array substrate according to claim 2 , wherein a width of the lightly doped drain region ranges from about 0.5 μm to about 1 μm.

4 . The array substrate according to claim 1 , wherein the array substrate further comprises:
a second insulating layer disposed between the active layer and the gate electrode; a via penetrating through the first insulating layer and the second insulating layer; and source/drain electrodes positioned on the first insulating layer, the source/drain electrodes in contact with the source/drain regions via the via.

5 . The array substrate according to claim 1 , wherein a doping concentration of the source/drain regions is greater than a doping concentration of the lightly doped drain region, and wherein the doping concentration of the source/drain regions ranges from about 4.5×10 15 to about 6×10 15 ions/cm 3 and the doping concentration of the lightly doped drain region ranges from about 5×10 12 to about 4.5×10 15 ions/cm 3 .

6 . The array substrate according to claim 1 , wherein the active layer comprises low-temperature polysilicon.

7 . A display panel comprising the array substrate according to claim 1 .

8 . A display device comprising the display panel according to claim 7 .

9 . A method for fabricating an array substrate, the method comprising:
forming an active layer on a substrate; forming a gate electrode and a first electrode on the active layer; forming a first insulating layer on the gate electrode and the first electrode; forming a barrier material layer on the first insulating layer; performing one patterning process on the barrier material layer to form a barrier and a second electrode, wherein a projection of the second electrode on the substrate at least partially overlaps a projection of the first electrode on the substrate, and wherein a projection of a portion of the barrier extending outward from a side of the gate electrode on the substrate is within a projection of a portion of the active layer extending outward from a side of the active layer on the substrate; and performing a first doping on the active layer by using the barrier as a mask to form source/drain regions on both sides of the channel region of the active layer and a lightly doped drain region between the channel region and the source/drain regions.

10 . The method for fabricating an array substrate according to claim 9 , wherein the barrier has an opening, and wherein a projection of the opening on the substrate at least partially overlaps a projection of the gate electrode on the substrate.

11 . The method for fabricating an array substrate according to claim 10 , wherein the width of the lightly doped drain region ranges from about 0.5 μm to about 1 μm.

12 . The method for fabricating an array substrate according to claim 9 , wherein a doping energy of the first doping is about 30 Kev˜40 Kev.

13 . The method for fabricating an array substrate according to claim 9 , wherein a doping concentration of the source/drain regions is greater than a doping concentration of the lightly doped drain region, wherein the doping concentration of the source/drain regions is about 4.5×10 15 to about 6×10 15 ions/cm 3 , and wherein the doping concentration of the lightly doped drain region is about 5×10 12 to about 4.5×10 15 ions/cm 3 .

14 . The method for fabricating an array substrate according to claim 9 , wherein a conductivity type of the channel region is N-type, and wherein a conductivity type of the lightly doped drain region and a conductivity type of doping regions of the source/drain regions are P type.

15 . The method for fabricating an array substrate according to claim 9 , wherein the method for fabricating the array substrate further comprises:
before forming the gate electrode and the first electrode, forming a second insulating layer on the active layer; after forming the source/drain regions, forming a via penetrating through the first insulating layer and the second insulating layer, and forming source/drain electrodes on the first insulating layer, wherein the source/drain electrodes are in contact with the source/drain regions through the via

16 . The method for fabricating an array substrate according to claim 15 , wherein forming the gate electrode and the first electrode comprises:
forming a gate electrode material layer on the second insulating layer; and patterning the gate electrode material layer to form the gate electrode and the first electrode.

17 . The method for fabricating an array substrate according to claim 1 , wherein the method for fabricating the array substrate further comprises:
after forming the gate electrode and the first electrode, doping the active layer by using the gate electrode as a mask to define a channel region of the active layer.

18 . A display panel comprising the array substrate according to claim 2 .

19 . A display panel comprising the array substrate according to claim 3 .

20 . A display panel comprising the array substrate according to claim 4 .

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Li Zihua
• Liu Jing
• Liu Qi
• Ma Qun

Classifications

• H01L27/1288

  Electricity · mapped topic

• H01L27/127

  Electricity · mapped topic

• H01L27/1222 Primary

  Electricity · mapped topic

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/0221 Primary

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title