Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2019341504-A1
Application number	US-201816165885-A
Country	US
Kind code	A1
Filing date	Oct 19, 2018
Priority date	May 4, 2018
Publication date	Nov 7, 2019
Grant date	—

Abstract

A semiconductor device may include an n− type of layer disposed at a first surface of a substrate; a p− type of region and a p+ type of region disposed at a top portion of the n− type of layer; a first electrode disposed on the p− type of region and the p+ type of region; and a second electrode disposed at a second surface of the substrate, wherein the first electrode includes a first metal layer disposed on the p− type of region and a second metal layer disposed on the first metal layer, and the first metal layer is in continuous contact with the p− type of region.

First claim

What is claimed is:

1 . A semiconductor device comprising:
an n− type of layer disposed at a first surface of a substrate; a p− type of region and a p+ type of region disposed at a top portion of the n− type of layer; a first electrode disposed on the p− type of region and the p+ type of region; and a second electrode disposed at a second surface of the substrate, wherein the first electrode includes a first metal layer disposed on the p− type of region and a second metal layer disposed on the first metal layer, and wherein the first metal layer is in continuous contact with the p− type of region.

2 . The semiconductor device of claim 1 , wherein an ion doping concentration of the p+ type of region is higher than an ion doping concentration of the p− type of region.

3 . The semiconductor device of claim 2 , wherein the p− type of region and the p+ type of region are in contact with each other.

4 . The semiconductor device of claim 3 , wherein a thickness of the p+ type of region between the substrate and the first electrode is thicker than a thickness of the p− type of region between the substrate and the first electrode.

5 . The semiconductor device of claim 4 ,
wherein the first metal layer includes a Schottky metal, and wherein the second metal layer and the second electrode include an ohmic metal.

6 . The semiconductor device of claim 5 , wherein the first metal layer is disposed and extends on the p+ type of region.

7 . The semiconductor device of claim 6 , wherein the first metal layer is in contact with the p− type of region to form a Schottky junction in a boundary surface therebetween, and is in contact with the p+ type of region to form an ohmic junction in a boundary surface therebetween.

8 . The semiconductor device of claim 5 , wherein the second metal layer is disposed on the p+ type of region.

9 . The semiconductor device of claim 8 ,
wherein the first metal layer is in contact with the p− type of region to form a Schottky junction in a boundary surface therebetween, and wherein the second metal layer is in contact with the p+ type of region to form an ohmic junction in a boundary surface therebetween.

10 . The semiconductor device of claim 1 , wherein the substrate is an n+ type of silicon carbide substrate.

11 . A method for manufacturing a semiconductor device, the method comprising:
forming an n− type of layer in a first surface of a substrate; forming a p− type of region and a p+ type of region in a top portion of the n− type of layer; forming a first electrode on the p− type of region and the p+ type of region; and forming a second electrode in a second surface of the substrate, wherein the first electrode includes a first metal layer disposed on the p− type of region and a second metal layer disposed on the first metal layer, and wherein the first metal layer is in continuous contact with the p− type of region.

12 . The method of claim 11 , wherein an ion doping concentration of the p+ type of region is higher than an ion doping concentration of the p− type of region.

13 . The method of claim 12 , wherein the p− type of region and the p+ type of region are in contact with each other.

14 . The method of claim 13 , wherein a thickness of the p+ type of region between the substrate and the first electrode is thicker than a thickness of the p− type of region between the substrate and the first electrode.

15 . The method of claim 14 ,
wherein the first metal layer includes a Schottky metal, and wherein the second metal layer and the second electrode include an ohmic metal.

16 . The method of claim 15 , wherein the first metal layer is disposed and extends on the p+ type of region.

17 . The method of claim 16 , wherein the first metal layer is in contact with the p− type of region to form a Schottky junction in a boundary surface therebetween, and is in contact with the p+ type of region to form an ohmic junction in a boundary surface therebetween.

18 . The method of claim 15 , wherein the second metal layer is disposed on the p+ type of region.

19 . The method of claim 18 ,
wherein the first metal layer is in contact with the p− type of region to form a Schottky junction in a boundary surface therebetween, and wherein the second metal layer is in contact with the p+ type of region to form an ohmic junction in a boundary surface therebetween.

20 . The method of claim 11 , wherein the substrate is an n+ type of silicon carbide substrate.

Assignees

• Hyundai Motor Co Ltd
• Kia Motors Corp

Inventors

• Joo Nackyong
• Jung Youngkyun
• Park Junghee
• Lee Jongseok
• Chun Dae Hwan

Classifications

• H10P14/2904

  Silicon carbide · CPC title

• H10D64/0123 Primary

  to silicon carbide · CPC title

• H10D64/0115

  to silicon carbide · CPC title

• H01L29/0834

  Electricity · mapped topic

• H01L29/47

  Electricity · mapped topic