Shift register units, gate scanning circuits, driving methods and display apparatuses

Patent metadata

Field	Value
Publication number	US-2019340967-A1
Application number	US-201715751120-A
Country	US
Kind code	A1
Filing date	Jul 24, 2017
Priority date	Sep 30, 2016
Publication date	Nov 7, 2019
Grant date	—

Abstract

The present disclosure provides a shift register unit, a gate scanning circuit, a driving method, and a display apparatus. The shift register unit comprises a reset circuit configured to transmit a signal from a signal control terminal to a first node and a shift register unit signal output terminal under the control of a reset control signal input terminal; a first pull-down control circuit configured to transmit the signal from the signal control terminal to the first node and the shift register unit signal output terminal under the control of a second node; and a second pull-down control circuit configured to transmit the signal from the signal control terminal to the first node and the shift register unit signal output terminal under the control of a third node control signal input terminal coupled to a third node, so as to cooperate with the reset circuit and the first pull-down control circuit to jointly reset the shift register unit in a phase in which output of the shift register unit should not occur, thereby effectively preventing output of the shift register unit from occurring in the phase in which output of the shift register unit should not occur.

First claim

1 . A gate scanning circuit, comprising:
a plurality of cascaded shift register units, each of which comprises:
an output circuit coupled to a first node, a first clock signal input terminal, and a shift register unit output terminal, and configured to transmit a signal from the first clock signal input terminal to the shift register unit output terminal under the control of the first node;
an input circuit coupled to the first node and a shift register unit input terminal, and configured to transmit a signal from the shift register unit input terminal to the first node under the control of the shift register unit input terminal;
a reset circuit coupled to a reset control signal input terminal, the first node, the shift register unit signal output terminal, and a signal control terminal, and configured to transmit a signal from the signal control terminal to the first node and the shift register unit signal output terminal under the control of the reset control signal input terminal;
a first pull-down control circuit coupled to a second node, the first node, the shift register unit signal output terminal, and the signal control terminal, and configured to transmit the signal from the signal control terminal to the first node and the shift register unit signal output terminal under the control of the second node;
a second pull-down control circuit coupled to a third node, the first node, the shift register unit signal output terminal, and the signal control terminal, and configured to transmit the signal from the signal control terminal to the first node and the shift register unit signal output terminal under the control of the third node; and
a second node control circuit coupled to the first node, the second node, a second clock signal input terminal, and the signal control terminal, and configured to output the signal from the signal control terminal or a signal from the second clock signal input terminal to the second node under the control of the first node and the second clock signal input terminal; and
a plurality of clock signal lines, wherein each of the shift register units at odd-numbered stages has a first clock signal input terminal coupled to a first clock signal line, and a second clock signal input terminal coupled to a second clock signal line; and each of the shift register units at even-numbered stages has a first clock signal input terminal coupled to the second clock signal line, and a second clock signal input terminal coupled to the first clock signal line; and wherein in shift register units at two adjacent stages, the shift register unit at a previous stage has a shift register unit output terminal coupled to a shift register unit input terminal of the shift register unit at a next stage, a reset control signal input terminal coupled to a shift register unit output terminal of the shift register unit at the next stage, and a third node coupled to a second node of the shift register unit at the next stage.

2 - 10 . (canceled)

11 . A driving method for driving the gate scanning circuit according to claim 1 , the driving method comprising:
in an auxiliary reset phase, resetting, by a third node of a shift register unit at an n th stage, the shift register unit at the n th stage under the control of a second node of a shift register unit at an (n+1) th stage, where n is a positive integer.

12 . The driving method according to claim 11 , further comprising:
in a first phase, for the shift register unit at the n th stage, inputting a high level to its shift register unit input terminal, inputting a low level to its first clock signal input terminal, inputting a high level to its second clock signal input terminal, inputting a low level to its signal control terminal, inputting a low level to its reset control signal input terminal, and inputting a low level to the third node, so that a low level is output by the shift register unit output terminal at the n th stage.

13 . The driving method according to claim 11 , further comprising:
in a second phase, for the shift register unit at the n th stage, inputting a low level to its shift register unit input terminal, inputting a high level to its first clock signal input terminal, inputting a low level to its second clock signal input terminal, inputting a low level to its signal control terminal, inputting a low level to its reset control signal input terminal, and inputting a low level to the third node, so that a high level is output by the shift register unit output terminal at the n th stage.

14 . The driving method according to claim 11 , further comprising:
in a third phase, for the shift register unit at the n th stage, inputting a low level to its shift register unit input terminal, inputting a low level to its first clock signal input terminal, inputting a high level to its second clock signal input terminal, inputting a low level to its signal control terminal, inputting a high level to its reset control signal input terminal, and inputting a low level to the third node, so that a low level is output by the shift register unit output terminal at the n th stage.

15 . The driving method according to claim 12 , wherein the step of in the auxiliary reset phase, resetting, by the third node of the shift register unit at the n th stage, the shift register unit at the n th stage under the control of the second node of the shift register unit at the (n+1) th stage comprises:
for the shift register unit at the n th stage, inputting a low level to its shift register unit input terminal, inputting a high level to its first clock signal input terminal, inputting a low level to its second clock signal input terminal, inputting a low level to its signal control terminal, inputting a low level to its reset control signal input terminal, and inputting a high level to the third node, so that a low level is output by the shift register unit output terminal at the n th stage.

16 . A display apparatus, comprising the gate scanning circuit according to claim 1 .

17 . The driving method according to claim 12 , further comprising:
in a second phase, for the shift register unit at the n th stage, inputting a low level to its shift register unit input terminal, inputting a high level to its first clock signal input terminal, inputting a low level to its second clock signal input terminal, inputting a low level to its signal control terminal, inputting a low level to its reset control signal input terminal, and inputting a low level to the third node, so that a high level is output by the shift register unit output terminal at the n th stage.

18 . The driving method according to claim 13 , further comprising:
in a third phase, for the shift register unit at the nth stage, inputting a low level to its shift register unit input terminal, inputting a low level to its first clock signal input terminal, inputting a high level to its second clock signal input terminal, inputting a low level to its signal control terminal, inputting a high level to its reset control signal input terminal, and inputting a low level to the third node, so that a low level is output by the shift register unit output terminal at the n th stage.

19 . The driving method according to claim 17 , further comprising:
in a third phase, for the shift register unit at the nth stage, inputting a low level to its shift register unit input terminal, inputting a low level to its first clock signal input terminal, inputting a high level to its second clock signal input terminal, inputting a low level to its signal control terminal, inputting a high level to its reset control signal input terminal, and inputting a low level to the third node, so that a low le

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Zhang Xiaoxiang
• Chen Xi
• Liu Mingxuan
• Guo Huibin
• Luo Liping

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title