Quantum computer simulator characterization

Patent metadata

Field	Value
Publication number	US-2019340532-A1
Application number	US-201916401585-A
Country	US
Kind code	A1
Filing date	May 2, 2019
Priority date	May 2, 2018
Publication date	Nov 7, 2019
Grant date	—

Abstract

The disclosure describes various aspects of quantum computer simulators. In an aspect, a method for characterizing a quantum computer simulator includes identifying simulator processes supported by the quantum computer simulator, generating, for each simulator process, characteristic curves for different gates or quantum operations, the characteristic curves including information for predicting the time it takes to simulate each of the gates or quantum operations in a respective simulator process, and providing the characteristic curves to select one of the simulator processes to simulate a circuit, quantum program, or quantum algorithm that uses at least some of the gates or quantum operations. In another aspect, a method for optimizing simulations in a quantum computer simulator is described where a simulator process is selected for simulation of a circuit, quantum program, or quantum algorithm based on characteristic curves that predict a time it takes for the simulation to be carried out.

First claim

What is claimed is:

1 . A method for characterizing a quantum computer simulator, comprising identifying a plurality of simulator processes supported by the quantum computer simulator;
generating, for each simulator process, characteristic curves for each of a plurality of gates or quantum operations, the characteristic curves including information for predicting a time it takes to simulate each of the plurality of gates or quantum operations in a respective simulator process; and providing the characteristic curves for selection of one of the plurality of simulator processes to simulate a circuit, quantum program, or quantum algorithm that uses at least some of the plurality of gates or quantum operations.

2 . The method of claim 1 , wherein each simulator process includes an evaluation program running on separate hardware, the separate hardware having a specified hardware configuration, and the evaluation program being configured to perform a benchmarking functionality to generate the characteristic curves for each of the plurality of gates or quantum operations.

3 . The method of claim 1 , wherein the plurality of simulator processes include a plurality of different evaluation programs, each evaluation program running on separate hardware, and each of the separate hardware having a same hardware configuration.

4 . The method of claim 1 , wherein the plurality of simulator processes include a plurality of different evaluation programs, each evaluation program running on separate hardware, and each of the separate hardware having a different hardware configuration.

5 . The method of claim 1 , wherein the plurality of simulator processes include a plurality of hardware, each hardware having a different hardware configuration and running a same evaluation program.

6 . The method of claim 1 , wherein the plurality of simulator processes include at least a first plurality of hardware and a second plurality of hardware, each hardware in the first plurality of hardware having a same first configuration and running a different evaluation program, and each hardware in the second plurality of hardware having a same second configuration and running a different evaluation program.

7 . The method of claim 1 , wherein each simulator process includes an evaluation program running on separate hardware, the separate hardware being configured to include one or more of a graphic processing unit (GPU), a single-core central processing unit (CPU), a multi-core CPU, a tensor processing unit, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA)-based Ising model simulator.

8 . The method of claim 1 , wherein generating the characteristic curves for each of the plurality of gates or quantum operations includes generating the characteristic curves based on one or more of the gates or quantum operations under consideration, the number of control qubits for the gate or quantum operation, or the number of system qubits within a range of system qubits supported by the quantum computer simulator.

9 . The method of claim 1 , wherein generating the characteristic curves for each of the plurality of gates or quantum operations includes:
in an evaluation program of the simulator process, running one of the plurality of gates or quantum operations multiple times to determine an average time it takes to simulate that particular gate or quantum operation in that particular simulator process.

10 . The method of claim 9 , wherein the number of gate or quantum operation repetitions is based at least in part on minimizing a contribution, on the average time, of an overhead associated with simulating the circuit, quantum program, or quantum algorithm.

11 . The method of claim 1 , wherein generating the characteristic curves for each of the plurality of gates or quantum operations includes:
identifying a trend based on a number of system qubits under consideration; and limiting, when the trend is identified, information that is needed to complete the characteristic curves to reduce an amount of time it takes to generate the characteristic curves.

12 . The method of claim 11 , wherein identifying the trend includes identifying that considering an additional system qubit doubles a time to simulate a particular gate or quantum operation.

13 . The method of claim 11 , wherein identifying the trend includes identifying that a simulation of one of the plurality of gates or quantum operations is equivalent to a simulation of that particular gate or quantum operation using fewer controls and fewer system qubits.

14 . The method of claim 1 , wherein providing the characteristic curves includes organizing information in the characteristic curves into one or more tables accessible by the quantum computer simulator.

15 . The method of claim 1 , wherein generating the characteristic curves for each of the plurality of gates or quantum operations includes:
mapping the characteristic curves associated with a first simulator process of the plurality of simulator processes to a second simulator process of the plurality of simulator processes when an evaluation program and hardware configuration of hardware used for the second simulator process is the same as the evaluation program and hardware configuration of hardware used for the first simulator process.

16 . A method for optimizing simulations in a quantum computer simulator, comprising:
receiving a circuit, quantum program, or quantum algorithm for simulation by the quantum computer simulator; selecting for simulation of the circuit, quantum program, or quantum algorithm, a simulator process from a plurality of simulator processes supported by the quantum computer simulator, the selection being based at least in part on characteristic curves that predict a time it takes to simulate gates or quantum operations in the circuit, quantum program, or quantum algorithm in each of the plurality of simulator processes; and providing an estimate of the time it will take to simulate the circuit, quantum program, or quantum algorithm by the simulator process.

17 . The method of claim 16 , wherein each simulator process includes an evaluation program running on separate hardware, the separate hardware having a specified hardware configuration, and the evaluation program being configured to perform a benchmarking functionality to generate the characteristic curves for each of the plurality of gates or quantum operations.

18 . The method of claim 16 , wherein the plurality of simulator processes include a plurality of different evaluation programs, each evaluation program running on separate hardware, and each of the separate hardware having a same hardware configuration.

19 . The method of claim 16 , wherein the plurality of simulator processes include a plurality of different evaluation programs, each evaluation program running on separate hardware, and each of the separate hardware having a different hardware configuration.

20 . The method of claim 16 , wherein the plurality of simulator processes include a plurality of hardware, each hardware having a different hardware configuration and running a same evaluation program.

21 . The method of claim 16 , wherein the plurality of simulator processes include at least a first plurality of hardware and a second plurality of hardware, each hardware in the first plurality of hardware having a same first configuration and running a different evaluation program, and each hardware in the second p

Assignees

• Ionq Inc

Inventors

• Ducore Andrew Maps
• Nam Yuensong
• Shehab Omar
• Keesan Matthew Joseph
• Allen Stewart O

Classifications

• G06N5/01

  Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F8/443

  Optimisation · CPC title

• G06N10/00 Primary

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• G06F17/5009

  Physics · mapped topic