System, method and computer-accessible medium for satisfiability attack resistant logic locking

Patent metadata

Field	Value
Publication number	US-2019340394-A1
Application number	US-201716087911-A
Country	US
Kind code	A1
Filing date	Mar 20, 2017
Priority date	Mar 22, 2016
Publication date	Nov 7, 2019
Grant date	—

Abstract

Exemplary embodiment of the present disclosure can include, for example, a logic-locking circuit (“SARLock”), which can include a logic cone(s) receiving a distinguishing input pattern(s) (DIP), a comparator(s) receiving the DIP(s) and a key value(s), and a logic gate(s) connected to an output of the logic cone and to an output of the comparator. A mask(s) can be connected to the comparator(s) and the logic gate(s). The logic gate(s) can be a XOR gate(s). The comparator(s) can be configured to flip a signal(s) based on a combination of the DIP(s) and the key value(s). A mask(s) can be connected to the comparator(s) and the logic gate(s), which can be configured to prevent the flipped signal(s) from being asserted for a correct key value(s).

First claim

1 . A logic-locking circuit, comprising:
at least one logic cone receiving at least one distinguishing input pattern (DIP); at least one comparator receiving the at least one DIP and at least one key value; and at least one logic gate connected to an output of the at least one logic cone and to an output of the at least one comparator, and configured to corrupt the output of the at least one logic cone for at most a predetermined constant number of DIPs for every incorrect key value.

2 . The logic-locking circuit of claim 1 , further comprising at least one mask connected to the at least one comparator and the at least one logic gate.

3 . The logic-locking circuit of claim 1 , wherein the at least one logic gate is at least one XOR gate.

4 . The logic-locking circuit of claim 1 , wherein the at least one comparator is configured to flip at least one input signal to the at least one comparator based on a combination of the at least one DIP and the at least one key value.

5 . The logic-locking circuit of claim 4 , further comprising at least one mask connected to the at least one comparator and the at least one logic gate.

6 . The logic-locking circuit of claim 5 , wherein the at least one mask is configured to prevent the at least one flipped signal from being asserted for a correct at least one key value.

7 . The logic-locking circuit of claim 1 , further comprising at least one miter-like circuit configured to determine the at least one DIP.

8 . The logic-locking circuit of claim 1 , further comprising at least one scrambler connected to an input of the at least one comparator.

9 . The logic-locking circuit of claim 8 , wherein the at least one scrambler is configured to provide the at least one key value to the at least one comparator.

10 . The logic-locking circuit of claim 9 , wherein the at least one scrambler is further configured to corrupt an output of the at least one comparator for an incorrect key combination.

11 . A method for logic locking of at least one circuit, comprising:
receiving at least one distinguishing input pattern (DIP) and at least one key value thereto using at least one comparator of at least one logic-locking circuit, wherein the at least one logic-locking circuit includes at least one logic gate connected to an output of the at least one comparator; and limiting a discriminating ability of every one of the DIP to a predetermined constant number of incorrect keys.

12 . The method of claim 11 , wherein the at least one logic-locking circuit further includes at least one masking unit between the at least one comparator and the at least one logic gate.

13 . The method of claim 11 , wherein the at least one logic gate includes at least one XOR gate.

14 . The method of claim 11 , wherein the at least one DIP is received by at least one logic cone.

15 . The method of claim 14 , further comprising corrupting an output of the at least one logic cone for at most a further predetermined constant number of DIPs for every incorrect key value.

16 . The method of claim 15 , wherein the output of the at least one logic cone is corrupted using the at least one logic gate.

17 . The method of claim 11 , further comprising flipping at least one input signal to the at least one comparator based on a combination of the at least one DIP and the at least one key value.

18 . The method of claim 17 , further comprising preventing the at least one flipped signal from being asserted for a correct at least one key value.

19 . The method of claim 11 , further comprising determining the at least one DIP using at least one miter-like circuit.

20 . The method of claim 11 , further comprising scrambling at least one input to the at least one comparator, and corrupting an output of the at least one comparator for an incorrect key combination.

21 . A system for logic locking of at least one circuit, comprising:
a computer hardware arrangement configured to:
receive at least one distinguishing input pattern (DIP) and at least one key value thereto using at least one comparator of at least one logic-locking circuit, wherein the at least one logic-locking circuit includes at least one logic gate connected to an output of the at least one comparator; and
limit a discriminating ability of every one of the DIP to a predetermined constant number of incorrect keys.

22 - 30 . (canceled)

31 . A non-transitory computer-accessible medium having stored thereon computer-executable instructions for logic locking of at least one circuit, wherein, when a computer arrangement executes the instructions, the computer arrangement is configured to perform procedures: comprising:
receiving at least one distinguishing input pattern (DIP) and at least one key value thereto using at least one comparator of at least one logic-locking circuit, wherein the at least one logic-locking circuit includes at least one logic gate connected to an output of the at least one comparator; and limiting a discriminating ability of every one of the DIP to a predetermined constant number of incorrect keys.

32 - 40 . (canceled)

Assignees

• Univ New York

Inventors

• Sinanoglu Ozgur
• Yasin Muhammad
• Rajendran Jeyavijayan

Classifications

• G06F2115/08

  Intellectual property [IP] blocks or IP cores · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F21/72

  in cryptographic circuits · CPC title

• G06F21/75 Primary

  by inhibiting the analysis of circuitry or operation · CPC title

• G01R31/31719 Primary

  Security aspects, e.g. preventing unauthorised access during test · CPC title