True random number generator with dynamic compensation capability

Patent metadata

Field	Value
Publication number	US-2019339941-A1
Application number	US-201916404747-A
Country	US
Kind code	A1
Filing date	May 7, 2019
Priority date	May 7, 2018
Publication date	Nov 7, 2019
Grant date	—

Abstract

A true random number generator with a dynamic compensation capacity comprises a loop control logic, a shift register, a sensitive amplifier and a load matching unit. The sensitive amplifier comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor and two NMOS arrays. Each NMOS array comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor and a thirteenth NMOS transistor. The load matching unit comprises a first D flip-flop and a second D flip-flop and is configured at an output terminal and an inverted output terminal of the sensitive amplifier. The true random number generator has the advantages of simple feedback regulation and high robustness.

First claim

What is claimed is:

1 . A true random number generator with a dynamic compensation capacity, comprising:
a loop control logic; and a shift register used for storing output sequences, wherein the loop control logic comprises:
a clock terminal,
a data input terminal,
a first output terminal and
a second output terminal;
wherein the shift register comprises
a clock terminal,
a serial data input terminal; and
a 4-bit parallel data output terminal;
wherein the data input terminal of the loop control logic is connected to the 4-bit parallel data output terminal of the shift register and is used to acquire 4-bit output sequences stored in the shift register; the clock terminal of the loop control logic is connected to the clock terminal of the shift register, and a first clock signal is accessed to a connecting terminal of the clock terminal of the loop control logic and the clock terminal of the shift register, wherein the first output terminal of the loop control logic is used to output a first 5-bit parallel control signal, and the second output terminal of the loop control logic is used to output a second 5-bit parallel control signal, wherein the true random number generator with a dynamic compensation capacity further comprises a sensitive amplifier and a load matching unit, wherein the sensitive amplifier comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor and two NMOS arrays; each said NMOS array comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor and a thirteenth NMOS transistor, wherein a drain of the third NMOS transistor, a drain of the ninth NMOS transistor, a drain of the tenth NMOS transistor, a drain of the eleventh NMOS transistor, a drain of the twelfth NMOS transistor and a drain of the thirteenth NMOS transistor are connected, and a corresponding connecting terminal is an input/output terminal of the NMOS array, wherein a gate of the third NMOS transistor, a gate of the ninth NMOS transistor, a gate of the tenth NMOS transistor, a gate of the eleventh NMOS transistor, a gate of the twelfth NMOS transistor and a gate of the thirteenth NMOS transistor are connected, and a corresponding connecting terminal is a clock terminal of the NMOS array, wherein a source of the third NMOS transistor, a source of the fourth NMOS transistor, a source of the fifth NMOS transistor, a source of the sixth NMOS transistor, a source of the seventh NMOS transistor and a source of the eighth NMOS transistor are connected, and a corresponding connecting terminal is a ground terminal of the NMOS array, wherein a gate of the fourth NMOS transistor is a first configuration terminal of the NMOS array, a gate of the fifth NMOS transistor is a second configuration terminal of the NMOS array, a gate of the sixth NMOS transistor is a third configuration terminal of the NMOS array, a gate of the seventh NMOS transistor is a fourth configuration terminal of the NMOS array, and a gate of the eighth NMOS transistor is a fifth configuration terminal of the NMOS array, wherein a drain of the fourth NMOS transistor is connected to a source of the ninth NMOS transistor, a drain of the fifth NMOS transistor is connected to a source of the tenth NMOS transistor, a drain of the sixth NMOS transistor is connected to a source of the eleventh NMOS transistor, a drain of the seventh NMOS transistor is connected to a source of the twelfth NMOS transistor, and a drain of the eighth NMOS transistor is connected to a source of the thirteenth NMOS transistor; wherein a power supply is accessed to a source of the first PMOS transistor, a source of the second PMOS transistor, a source of the third PMOS transistor and a source of the fourth PMOS transistor, wherein a gate of the first PMOS transistor and a gate of the fourth PMOS transistor are connected to the clock terminals of the two NMOS arrays, and a corresponding connecting terminal is a clock terminal of the sensitive amplifier, wherein a second clock signal is accessed to the clock signal of the sensitive amplifier, and the first clock signal is a delay signal obtained after the second clock signal is delayed by three fourths of a cycle, wherein a drain of the first PMOS transistor, a drain of the second PMOS transistor, a drain of the first NMOS transistor, a gate of the second NMOS transistor and a gate of the third PMOS transistor are connected, and a corresponding connecting terminal is an inverted output terminal of the sensitive amplifier, wherein a drain of the third PMOS transistor, a drain of the fourth PMOS transistor, a gate of the second PMOS transistor, a gate of the first NMOS transistor and a drain of the second NMOS transistor are connected, and a corresponding connecting terminal is an output terminal of the sensitive amplifier, wherein a source of the first NMOS transistor is connected to the input/out terminal of the first NMOS array, and a source of the second NMOS transistor is connected to the input/output terminal of the second NMOS array, wherein the ground terminals of the two NMOS arrays are all grounded, wherein the first configuration terminal of the first NMOS array is a first control terminal of the sensitive amplifier and allows a first bit of the first 5-bit parallel control signal to be accessed thereto; the second configuration terminal of the first NMOS array is a second control terminal of the sensitive amplifier and allows a second bit of the first 5-bit parallel control signal to be accessed thereto; the third configuration terminal of the first NMOS array is a third control terminal of the sensitive amplifier and allows a third bit of the first 5-bit parallel control signal to be accessed thereto; the fourth configuration terminal of the first NMOS array is a fourth control terminal of the sensitive amplifier and allow a fourth bit of the first 5-bit parallel control signal to be accessed thereto; the fifth configuration terminal of the first NMOS array is a fifth control terminal of the sensitive amplifier and allows a fifth bit of the first 5-bit parallel control signal to be accessed thereto, wherein the first configuration terminal of the second NMOS array is a sixth control terminal of the sensitive amplifier and allows a first bit of the second 5-bit parallel control signal to be accessed thereto; the second configuration terminal of the second NMOS array is a seventh control terminal of the sensitive amplifier and allows a second bit of the second 5-bit parallel control signal to be accessed thereto; the third configuration terminal of the second NMOS array is an eighth control terminal of the sensitive amplifier and allows a third bit of the second 5-bit parallel control signal to be accessed thereto; the fourth configuration terminal of the second NMOS array is a ninth control terminal of the sensitive amplifier and allows a fourth bit of the second 5-bit parallel control signal to be accessed thereto; the fifth configuration terminal of the second NMOS array is a tenth control terminal of the sensitive amplifier and allow a fifth bit of the second 5-bit parallel control signal to be accessed thereto, wherein the load matching unit comprises a first D flip-flop and a second D flip-flop, wherein the first D flip-flop and the second D flip-flop each has a clock terminal, an input terminal and an output terminal; the input terminal of the first D flip-flop is an input terminal of the load matching unit, and the input terminal of the second D flip-flop is an inverted input terminal of the load matching unit; the clock terminal of the first D flip-flop is connected to the clock terminal of t

Assignees

• Univ Wenzhou

Inventors

• Wang Pengjun
• Li Zhen
• Li Gang
• Chen Bo

Classifications

• G06F7/588 Primary

  Random number generators, i.e. based on natural stochastic processes · CPC title

• H03K19/003

  Modifications for increasing the reliability {for protection} · CPC title

• H03K19/17704

  the logic functions being realised by the interconnection of rows and columns · CPC title

• G06F7/582 Primary

  Pseudo-random number generators · CPC title

• G06F9/30134

  Register stacks; shift registers · CPC title