Semiconductor processing chamber multistage mixing apparatus

Patent metadata

Field	Value
Publication number	US-2019333786-A1
Application number	US-201916448323-A
Country	US
Kind code	A1
Filing date	Jun 21, 2019
Priority date	Feb 15, 2018
Publication date	Oct 31, 2019
Grant date	—

Abstract

Exemplary semiconductor processing systems may include a processing chamber, and may include a remote plasma unit coupled with the processing chamber. Exemplary systems may also include a mixing manifold coupled between the remote plasma unit and the processing chamber. The mixing manifold may be characterized by a first end and a second end opposite the first end, and may be coupled with the processing chamber at the second end. The mixing manifold may define a central channel through the mixing manifold, and may define a port along an exterior of the mixing manifold. The port may be fluidly coupled with a first trench defined within the first end of the mixing manifold. The first trench may be characterized by an inner radius at a first inner sidewall and an outer radius, and the first trench may provide fluid access to the central channel through the first inner sidewall.

First claim

1 . A semiconductor processing system component comprising:
a mixing manifold characterized by a first end and a second end opposite the first end, wherein the mixing manifold defines a central channel through the mixing manifold, wherein the mixing manifold defines a port along an exterior of the mixing manifold, wherein the port is fluidly coupled with a first trench defined within the first end of the mixing manifold, wherein the first trench is characterized by an inner radius at a first inner sidewall and an outer radius, and wherein the first trench provides fluid access to the central channel through the first inner sidewall.

2 . The semiconductor processing system component of claim 1 , wherein the mixing manifold further comprises a second trench defined within the first end of the mixing manifold, wherein the second trench is located radially outward from the first trench, and wherein the port is fluidly coupled with the second trench.

3 . The semiconductor processing system component of claim 2 , wherein the second trench is characterized by an inner radius at a second inner sidewall, and wherein the second inner sidewall further defines the outer radius of the first trench.

4 . The semiconductor processing system component of claim 3 , wherein the second inner sidewall defines a plurality of apertures defined through the second inner sidewall and providing fluid access to the first trench.

5 . The semiconductor processing system component of claim 4 , wherein the second inner sidewall defines two apertures through the second inner sidewall.

6 . The semiconductor processing system component of claim 5 , wherein the first inner sidewall defines a plurality of apertures defined through the first inner sidewall, and wherein each aperture of the plurality of apertures defined through the second inner sidewall are radially offset from each aperture of the plurality of apertures defined through the first inner sidewall.

7 . The semiconductor processing system component of claim 5 , wherein the two apertures are defined through the second inner sidewall at opposite ends of a diameter through the second inner sidewall.

8 . The semiconductor processing system component of claim 7 , wherein the port is defined equidistantly between the two apertures defined through the second inner sidewall.

9 . The semiconductor processing system component of claim 1 , wherein the first inner sidewall defines a plurality of apertures defined through the first inner sidewall and providing fluid access to the central channel.

10 . The semiconductor processing system component of claim 9 , wherein at least three apertures are defined through the first inner sidewall, and wherein the apertures are distributed equidistantly about the first inner sidewall.

11 . The semiconductor processing system component of claim 9 , wherein the first inner sidewall comprises a chamfered edge from the first end of the mixing manifold.

12 . The semiconductor processing system component of claim 11 , wherein the plurality of apertures are defined through the chamfered edge of the first inner sidewall.

13 . The semiconductor processing system component of claim 12 , wherein the plurality of apertures are defined at an angle through the first inner sidewall extending in a direction from the first end of the mixing manifold to the central channel.

14 . The semiconductor processing system component of claim 1 , wherein the mixing manifold comprises nickel.

15 . The semiconductor processing system component of claim 14 , wherein the nickel is nickel plating.

16 . A semiconductor processing system component comprising:
a mixing manifold characterized by a first end and a second end opposite the first end, wherein the mixing manifold defines a central channel through the mixing manifold, wherein the mixing manifold defines a port along an exterior of the mixing manifold, wherein the port is fluidly coupled with a first trench defined within the first end of the mixing manifold, wherein the first trench is characterized by an inner radius at a first inner sidewall and an outer radius, wherein the first trench provides fluid access to the central channel through the first inner sidewall, and wherein the mixing manifold further comprises a second trench defined within the first end of the mixing manifold, wherein the second trench is located radially outward from the first trench, and wherein the port is fluidly coupled with the second trench.

17 . The semiconductor processing system component of claim 16 , wherein the second trench is characterized by an inner radius at a second inner sidewall, and wherein the second inner sidewall further defines the outer radius of the first trench.

18 . The semiconductor processing system component of claim 17 , wherein the second inner sidewall defines a plurality of apertures defined through the second inner sidewall and providing fluid access to the first trench.

19 . The semiconductor processing system component of claim 18 , wherein the second inner sidewall defines two apertures through the second inner sidewall, and wherein the first inner sidewall defines a plurality of apertures defined through the first inner sidewall, and wherein each aperture of the plurality of apertures defined through the second inner sidewall are radially offset from each aperture of the plurality of apertures defined through the first inner sidewall.

20 . A semiconductor processing system component comprising:
a mixing manifold characterized by a first end and a second end opposite the first end, wherein the mixing manifold defines a central channel through the mixing manifold, wherein the mixing manifold defines a port along an exterior of the mixing manifold, wherein the port is fluidly coupled with a first trench defined within the first end of the mixing manifold, wherein the first trench is characterized by an inner radius at a first inner sidewall and an outer radius, wherein the first trench provides fluid access to the central channel through the first inner sidewall, wherein the first inner sidewall defines a plurality of apertures defined through the first inner sidewall and providing fluid access to the central channel, and wherein at least three apertures are defined through the first inner sidewall, and wherein the apertures are distributed equidistantly about the first inner sidewall.

Assignees

• Applied Materials Inc

Inventors

• Samir Mehmet Tugrul
• Yang Dongqing

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P72/0421 Primary

  for drying etching · CPC title

• H01L21/67069 Primary

  Electricity · mapped topic

• B01F5/0077

  Operations & Transport · mapped topic

• H01L21/31116

  Electricity · mapped topic