Implementing a hybrid finfet device and nanowire device utilizing selective sgoi

Patent metadata

Field	Value
Publication number	US-2019288012-A1
Application number	US-201916430539-A
Country	US
Kind code	A1
Filing date	Jun 4, 2019
Priority date	Jun 30, 2015
Publication date	Sep 19, 2019
Grant date	—

Abstract

A silicon-on-insulator substrate which includes a semiconductor substrate, a buried oxide layer, and a semiconductor layer is provided. A hard mask layer is formed over a first region of the silicon-on-insulator substrate. A first silicon-germanium layer is epitaxially grown on the semiconductor layer within a second region of the silicon-on-insulator substrate. The second region is at least a portion of the semiconductor layer not covered by the hard mask layer. A thermal annealing process is performed, such that germanium atoms from the first silicon-germanium layer are migrated to the portion of the semiconductor layer to form a second silicon-germanium layer. The hard mask layer is removed. A layer of semiconductor material is epitaxially grown on top of the semiconductor layer and the second silicon-germanium layer, where the layer of semiconductor material composed of the same material as semiconductor layer.

First claim

What is claimed is:

1 . A method of forming a silicon-on-insulator substrate, the method comprising:
providing a silicon-on-insulator substrate, wherein the silicon-on-insulator substrate includes a semiconductor substrate, a buried oxide layer formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide layer; forming a hard mask layer over at least a first region of the silicon-on-insulator substrate; epitaxially growing a first silicon-germanium layer on the semiconductor layer within a second region of the silicon-on-insulator substrate, wherein the second region comprises at least a portion of the semiconductor layer not covered by the hard mask layer; performing a thermal annealing process to at least the second region of the silicon-on-insulator substrate, such that germanium atoms from the first silicon-germanium layer are migrated to the portion of the semiconductor layer within the second region, to form a second silicon-germanium layer; removing the hard mask layer; and epitaxially growing a layer of semiconductor material on top of the semiconductor layer and the second silicon-germanium layer, wherein the composition of the layer of semiconductor material is equal to the composition of the semiconductor layer.

2 . The method of claim 1 , wherein the thermal annealing process is performed at a temperature greater than or equal to 1000 degrees Celsius and less than or equal to 1200 degrees Celsius.

3 . The method of claim 2 , wherein the thermal anneal is performed in an oxidizing environment.

4 . The method of claim 2 , wherein the thermal anneal is performed in an inert environment.

5 . The method of claim 1 , wherein epitaxially growing the layer of semiconductor material on top of the semiconductor layer and the second silicon-germanium layer comprises performing a chemical vapor deposition process.

6 . The method of claim 1 , wherein the semiconductor substrate comprises silicon.

7 . The method of claim 1 , wherein the buried oxide layer comprises silicon oxide.

8 . The method of claim 1 , wherein the second silicon-germanium layer has a composition of at least 15 percent germanium.

9 . The method of claim 1 , wherein the first region serves as an active region for the formation of one or more finFET devices.

10 . The method of claim 1 , wherein the second region serves as an active region for the formation of one or more nanowire devices.

11 . A method comprising:
providing a silicon-on-insulator substrate; forming a hard mask layer over a first region of the silicon-on-insulator substrate; epitaxially growing a first silicon-germanium layer on a second region of the silicon-on-insulator substrate, wherein the second region is not covered by the hard mask layer; performing a thermal annealing process to the second region to form a second silicon-germanium layer; removing the hard mask layer; and epitaxially growing a layer of semiconductor material on top of the first region and the second region, wherein the composition of the layer of semiconductor material is equal to the composition of an exposed top layer of the first region.

12 . The method of claim 11 , further comprising:
forming a first plurality of fins within the first region, wherein:
the composition of each fin of the first plurality of fins is silicon; and
the first plurality of fins are formed via etching the first region.

13 . The method of claim 12 , further comprising:
forming a second plurality of fins within the second region, wherein:
the composition of each fin of the second plurality of fins includes a layer of silicon and a layer of silicon-germanium; and
the second plurality of fins are formed via etching the second region.

14 . The method of claim 11 , wherein the thermal annealing process is performed at a temperature greater than or equal to 1000 degrees Celsius and less than or equal to 1200 degree Celsius.

15 . The method of claim 11 , wherein the thermal annealing process is performed in an oxidizing environment.

16 . The method of claim 11 , wherein the thermal annealing process is performed in an inert environment.

17 . The method of claim 11 , wherein epitaxially growing the layer of semiconductor material on top of the first region and the second region comprises performing a chemical vapor deposition process.

18 . The method of claim 11 , wherein the second silicon-germanium layer has a composition of at least 15 percent germanium.

19 . A method comprising:
providing a semiconductor layer formed on a buried oxide layer; forming a hard mask layer over a first region of the semiconductor layer; epitaxially growing a first silicon-germanium layer on a second region of the semiconductor layer, wherein the second region is not covered by the hard mask layer; performing a thermal annealing process to the second region to form a second silicon-germanium layer within the semiconductor layer of the second region; removing the hard mask layer; epitaxially growing a layer of semiconductor material on top of the semiconductor layer of the first region and the second silicon-germanium layer, wherein the composition of the layer of semiconductor material is equal to the composition of the semiconductor layer of the first region; forming a first plurality of fins within the first region via etching the first region.

20 . The method of claim 19 , further comprising:
Forming a second plurality of fins within the second region via etching the second region.

Assignees

• IBM

Inventors

• Chang Josephine B
• Chang Leland
• Lauer Isaac
• Sleight Jeffrey W

Classifications

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title