Imaging systems with boosted control signals

Patent metadata

Field	Value
Publication number	US-2019281243-A1
Application number	US-201815918067-A
Country	US
Kind code	A1
Filing date	Mar 12, 2018
Priority date	Mar 12, 2018
Publication date	Sep 12, 2019
Grant date	—

Abstract

An image sensor may include an array of imaging pixels and row control circuitry that provides control signals to the array of imaging pixels. In order to enable the row control circuitry to provide control signals to the array of imaging pixels that have a voltage greater than the power supply voltage, the row control circuitry may include voltage booster circuitry. The voltage booster circuitry may include two amplifiers and may be operable in three different modes. In the first mode, only the second amplifier may be enabled and the output voltage may be between 0V and 2.0V. In the second mode, both the first and second amplifiers may be enabled and the output voltage may be between 2.0V and 2.8V. In the third mode, only the first amplifier may be enabled and the output voltage may be between 2.8V and 4.0V.

First claim

What is claimed is:

1 . An image sensor that includes an array of imaging pixels and row control circuitry, wherein the row control circuitry comprises booster circuitry and the booster circuitry comprises:
a first amplifier with first and second inputs and a first output; a first switch interposed between the first output and an output node; a second amplifier with third and fourth inputs and a second output; a second switch interposed between the second output and the output node; and a third switch that is interposed between the second output and the first switch.

2 . The image sensor defined in claim 1 , wherein the booster circuitry further comprises:
a fourth switch that is interposed between a power supply voltage and the first switch.

3 . The image sensor defined in claim 2 , wherein a first reference voltage is coupled to the first input of the first amplifier and wherein a second reference voltage is coupled to the third input of the second amplifier.

4 . The image sensor defined in claim 3 , wherein the booster circuitry is configured to operate in a first mode in which the second switch is closed, the first switch is open, and an output voltage at the output node is equal to the second reference voltage.

5 . The image sensor defined in claim 4 , wherein the booster circuitry is configured to operate in a second mode in which the output voltage is equal to a sum of the first reference voltage and the second reference voltage.

6 . The image sensor defined in claim 5 , wherein the booster circuitry is configured to operate in a third mode in which the first switch is closed, the second switch is open, and the output voltage at the output node is equal to a sum of the power supply voltage and the first reference voltage.

7 . The image sensor defined in claim 3 , wherein the first output of the first amplifier is coupled to a first node and wherein the booster circuitry further comprises:
a fifth switch that is interposed between the first node and ground; and a first capacitor that is interposed between the first node and the first switch.

8 . The image sensor defined in claim 7 , wherein the booster circuitry further comprises:
a second node that is coupled to the second input of the first amplifier; a sixth switch that is coupled between the second node and ground; and a second capacitor that is coupled to the second node.

9 . The image sensor defined in claim 8 , wherein the booster circuitry further comprises:
a seventh switch coupled between the second capacitor and the first switch.

10 . The image sensor defined in claim 9 , wherein the second output of the second amplifier is coupled to the fourth input of the second amplifier.

11 . The image sensor defined in claim 9 , wherein the booster circuitry further comprises:
a third node that is interposed between the second capacitor and the seventh switch; and an eighth switch that is coupled between the third node and a third reference voltage.

12 . An image sensor comprising:
an array of imaging pixels; column control and readout circuitry; and row control circuitry, wherein the row control circuitry comprises booster circuitry configured to output a voltage that is between a ground voltage and a first voltage that is higher than the ground voltage in a first mode, between the first voltage and a power supply voltage that is higher than the first voltage in a second mode, and between the power supply voltage and a second voltage that is higher than the power supply voltage in a third mode.

13 . The image sensor defined in claim 12 , wherein the booster circuitry comprises first and second amplifiers, wherein the second amplifier is enabled in the first mode and the first amplifier is disabled in the first mode.

14 . The image sensor defined in claim 13 , wherein the first and second amplifiers are both enabled in the second mode.

15 . The image sensor defined in claim 14 , wherein the first amplifier is enabled in the third mode and the second amplifier is disabled in the third mode.

16 . A method of operating booster circuitry in an imaging sensor, wherein the booster circuitry comprises a first amplifier with a first input that receives a first reference voltage, a second amplifier with a second input that receives a second reference voltage, a first switch that is interposed between the first amplifier and an output node, and a second switch that is interposed between the second amplifier and the output node, the method comprising;
while the second amplifier is enabled, the first switch is open, and the second switch is closed, pre-charging the output node to the second reference voltage; and while the first amplifier is enabled, the first switch is closed, and the second switch is open, boosting the output node to a total output voltage that is equal to a sum of the first reference voltage and the second reference voltage.

17 . The method defined in claim 16 , wherein the booster circuitry further comprises a third switch that is interposed between an output of the second amplifier and the first switch and wherein pre-charging the output node to the second reference voltage comprises pre-charging the output node to the second reference voltage while the third switch is closed.

18 . The method defined in claim 17 , wherein the first amplifier has a second input, wherein the booster circuitry further comprises a capacitor that is interposed between the second input of the first amplifier and a fourth switch, wherein the fourth switch is interposed between capacitor and the first switch, and wherein pre-charging the output node to the second reference voltage comprises pre-charging the output node to the second reference voltage while the fourth switch is closed.

19 . The method defined in claim 18 , wherein the booster circuitry further comprises a fifth switch that is interposed between an output of the first amplifier and ground, wherein pre-charging the output node to the second reference voltage comprises pre-charging the output node to the second reference voltage while the fifth switch is closed, and wherein boosting the output node to the total output voltage comprises boosting the output node to the total output voltage while the fifth switch is open.

20 . The method defined in claim 19 , wherein the booster circuitry further comprises a sixth switch that is interposed between the second input of the first amplifier and ground, wherein pre-charging the output node to the second reference voltage comprises pre-charging the output node to the second reference voltage while the sixth switch is closed, and wherein boosting the output node to the total output voltage comprises boosting the output node to the total output voltage while the sixth switch is open.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Gurindagunta Sundaraiah
• Balar Bharat

Classifications

• G05F1/59 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H04N25/709 Primary

  Circuitry for control of the power supply · CPC title

• H04N5/378 Primary

  Electricity · mapped topic

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title