Neuromorphic system with transposable memory and virtual look-up table

Patent metadata

Field	Value
Publication number	US-2019279079-A1
Application number	US-201916276452-A
Country	US
Kind code	A1
Filing date	Feb 14, 2019
Priority date	Mar 8, 2018
Publication date	Sep 12, 2019
Grant date	—

Abstract

Provided is a technology for reducing hardware cost and enabling on-chip learning in a neuromorphic system. A synapse array includes a plurality of synapse circuits, and at least one of the plurality of synapse circuits includes at least bias transistor and a switch connected in series. Synapse circuits in the same row and column direction of the synapse array are connected to each other through a shared membrane line, and a charge amount proportional to a multiplication accumulation operation required for a forward or backward operation is supplied through the membrane line and is converted into a final digital value for output through an analog to digital converter. A virtual look-up table performs in advance a calculation required for a synapse weight update for learning of at least one column of the synapse array and is updated, so that the amount of a calculation required for entire learning is reduced.

First claim

What is claimed is:

1 . A neuromorphic system with a transposable memory and a virtual look-up table, comprising:
a multi-bit synapse array including a plurality of synapse circuits based on a SRAM structure; an analog to digital converter that converts a voltage charged in a membrane line by charge supplied according to a multiplication accumulation operation result in the multi-bit synapse array into a digital value; a pulse width modulation circuit that generates a pulse width modulation signal having a duty ratio proportional to a multi-bit digital input value and outputs the pulse width modulation signal to the multi-bit synapse array; and a neuronal processor that receives output data of the analog to digital converter, outputs the multi-bit digital input value, transfers forward and backward input values supplied from an exterior to the multi-bit synapse array, applies a nonlinear function to the multiplication accumulation operation result so as to perform processing required after a multiplication accumulation operation of an artificial neural network, and updates a synapse weight value of the multi-bit synapse array in a direction in which an error is reduced using a learning algorithm.

2 . The neuromorphic system with the transposable memory and the virtual look-up table according to claim 1 , wherein at least one of the plurality of synapse circuits comprises:
transistors for a current source each having one terminal connected to a power supply voltage and a gate supplied with a bias voltage for a forward operation or a bias voltage for a backward operation; a transistor for a switch connected between the other terminal of the transistor for a current source and a membrane line; and a NAND gate that controls a switching operation of the transistor for a switch.

3 . The neuromorphic system with the transposable memory and the virtual look-up table according to claim 2 , wherein the NAND gate has one terminal connected to an output terminal of a SRAM, the other terminal supplied with a pulse width modulation signal having a duty ratio proportional to a forward or backward input value, and an output terminal connected to a gate of the transistor for a switch.

4 . The neuromorphic system with the transposable memory and the virtual look-up table according to claim 2 , wherein the transistor for a switch transfers charge supplied from the transistor for a current source to the membrane line in an on state.

5 . The neuromorphic system with the transposable memory and the virtual look-up table according to claim 2 , wherein the transistors for a current source separately exist or are shared as one for the forward operation and the backward operation of the neuromorphic system.

6 . The neuromorphic system with the transposable memory and the virtual look-up table according to claim 1 , wherein the membrane line is connected to the synapse circuit arranged in a row and a column on the multi-bit synapse array.

7 . The neuromorphic system with the transposable memory and the virtual look-up table according to claim 1 , wherein the membrane line is arranged by one or by the number of bits of a synapse through synapse sharing.

8 . The neuromorphic system with the transposable memory and the virtual look-up table according to claim 1 , wherein the analog to digital converter comprises:
a pulse generator that generates pulses according to a charge voltage accumulated and charged in a parasitic capacitor existing on the membrane line; and a digital counter that counts the number of pulses outputted from the pulse generator and outputs a digital value according to the counted number.

9 . The neuromorphic system with the transposable memory and the virtual look-up table according to claim 8 , wherein the pulse generator comprises:
a comparator that compares the voltage charged in the parasitic capacitor with a reference voltage and generates a pulse according to the comparison result; and a transistor for reset that resets the voltage charged in the parasitic capacitor whenever “high” is outputted from the comparator.

10 . The neuromorphic system with the transposable memory and the virtual look-up table according to claim 9 , wherein the comparator includes a plurality of inverters connected in series.

11 . The neuromorphic system with the transposable memory and the virtual look-up table according to claim 1 , wherein the neuronal processor comprises:
a decoder that outputs a corresponding address value by using all or partial bits of a column component used in order to calculate a synapse update change amount as input; a virtual look-up table that stores a calculation value related to the synapse update change amount by using all bits or only partial bits of the column component on the basis of a row component required for calculating the synapse update change amount and the corresponding address value and stores a calculation value generated again whenever the row component is changed; a demultiplexer that distributes output of the virtual look-up table to two paths according to a batch signal indicating whether batch learning is performed and outputs the output; an accumulator that accumulates the output of the virtual look-up table; and a tri-level function unit that receives output of the demultiplexer and output of the accumulator and outputs the synapse update change amount as three levels of information.

12 . The neuromorphic system with the transposable memory and the virtual look-up table according to claim 11 , wherein the demultiplexer transfers the output of the virtual look-up table to the tri-level function unit when a control signal of “low” is supplied and transfers the output of the virtual look-up table to the accumulator when a control signal of “high” is supplied.

13 . The neuromorphic system with the transposable memory and the virtual look-up table according to claim 11 , wherein the tri-level function unit receives an accumulated synapse update change amount or the synapse update change amount as input, outputs 1 when the input is larger than 0, outputs −1 when the input is smaller than 0, and outputs 0 when the input is 0.

14 . The neuromorphic system with the transposable memory and the virtual look-up table according to claim 1 , wherein the neuromorphic system adds the synapse update change amount to a synapse weight stored in the multi-bit synapse array and updates the synapse weight in a row-by-row manner.

Assignees

• Postech Acad Ind Found

Inventors

• Sim Jae Yoon
• Cho Hwa Suk
• Son Hyun Woo

Classifications

• G06N3/065 Primary

  Analogue means · CPC title

• G06N3/08 Primary

  Learning methods · CPC title

• G06N3/048

  Activation functions · CPC title

• G06N20/00

  Machine learning · CPC title

• G06F1/03

  working, at least partly, by table look-up (G06F1/025 takes precedence) · CPC title