Inserting Null Vectors nto a Stream of Vectors

Patent metadata

Field	Value
Publication number	US-2019278597-A1
Application number	US-201916420467-A
Country	US
Kind code	A1
Filing date	May 23, 2019
Priority date	Jul 15, 2013
Publication date	Sep 12, 2019
Grant date	—

Abstract

Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array, a null vector count (N), and a selected dimension. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. N null stream vectors are inserted into the stream of vectors for the selected dimension without fetching respective null data from the memory.

First claim

1 . A method of operating a streaming engine in a computer system, the method comprising:
receiving stream parameters into control logic of the streaming engine to define a multidimensional array, wherein the stream parameters define a size for each dimension of the multidimensional array and a null vector count (N); fetching data from a memory coupled to the streaming engine responsive to the stream parameters; forming a stream of vectors for the multidimension array responsive to the stream parameters from the data fetched from memory; and forming N null stream vectors for the stream of vectors without fetching respective null data from the memory.

2 . The method of claim 1 , in which the stream parameters define a selected dimension of the multidimensional array, and in which the N null stream vectors are formed in the selected dimension of the stream of vectors.

3 . The method of claim 1 , in which the stream parameters include an element size of the array, a number of elements to include in each stream vector, and a number of stream vectors to include in the stream for each dimension of the array.

4 . The method of claim 1 , in which all elements in a null stream vector have a value of zero.

5 . The method of claim 1 , further comprising suppressing access to an address lookaside buffer while forming the N null vectors.

6 . The method of claim 1 , in which elements in a null stream vector have a null value that is specified by the stream parameters.

7 . A system comprising:
a system memory; a streaming engine coupled to the system memory, wherein the streaming engine comprises: a stream template register to hold stream parameters, wherein the stream parameters define a size for each dimension of the multidimensional array and a null vector count (N); address generation logic coupled to the stream template register; a memory interface logic coupled to receive a stream of address from the address generation logic and coupled to access the system memory; and control logic coupled to memory interface to insert N null stream vectors into a stream of vectors without fetching respective null data from the system memory.

8 . The system of claim 7 , wherein the control logic is operable to suppress a respective access to the system memory responsive to the stream parameters while inserting the N null stream vectors into the stream of vectors.

9 . The system of claim 7 , further comprising a translation lookaside buffer coupled to the address generation logic, wherein the control logic is operable to suppress an access to the translation lookaside buffer by the address generation logic while inserting the N null stream vectors into the stream of vectors.

10 . The system of claim 7 , in which all elements in a null stream vector have a value of zero.

11 . The system of claim 7 , in which elements in a null stream vector have a null value that is specified by the stream parameters.

12 . The system of claim 7 , further comprising:
a register file with inputs coupled to receive a vector fetched from the system memory; and an alignment network with inputs coupled to outputs of the register file, the alignment network coupled to the control logic for control, the alignment network having outputs coupled to outputs of the streaming engine to provide the N null stream vectors responsive to the stream parameters.

13 . The system of claim 7 being a system on a chip (SoC), further comprising a processing unit coupled to the outputs of the streaming engine to receive the stream vectors.

14 . A system comprising:
a system memory; a streaming engine coupled to access the system memory to form a stream of stream vectors, wherein the streaming engine is operable to insert a specified null vector count (N) of null stream vectors into the stream of stream vectors; and a processing unit coupled to outputs of the streaming engine to receive the stream of stream vectors.

15 . The system of claim 14 , in which the streaming engine comprises:
a stream template register to hold stream parameters, wherein the stream parameters define a size for each dimension of the multidimensional array and the null vector count N; and control logic coupled to receive the stream parameters from the stream template being operable to insert the N null stream vectors into the stream of vectors.

16 . The system of claim 15 , further comprising:
address generation logic coupled to the stream template register; a memory interface logic coupled to receive a stream of address from the address generation logic and coupled to access the system memory; and wherein the control logic is operable to suppress an access to the system memory responsive to the stream parameters while inserting the N null stream vectors into the stream of vectors.

17 . The system of claim 16 , further comprising a translation lookaside buffer coupled to the address generation logic, wherein the control logic is operable to suppress an access to the translation lookaside buffer by the address generation logic while inserting the N null stream vectors into the stream of vectors.

18 . The system of claim 14 , in which all elements in a null stream vector have a value of zero.

19 . The system of claim 14 , in which elements in a null stream vector have a null value that is specified by the stream parameters.

20 . The system of claim 14 , further comprising:
a register file with inputs coupled to receive a vector fetched from the system memory; and an alignment network with inputs coupled to outputs of the register file, the alignment network coupled to the control logic for control, the alignment network having outputs coupled to outputs of the streaming engine to provide the N null stream vectors responsive to the stream parameters.

Assignees

• Texas Instruments Inc

Inventors

• Bhardwaj Asheesh
• Leven William Franklin
• Tran Son Hung
• Anderson Timothy David

Classifications

• G06F12/0897

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/10

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F9/3822

  Parallel decoding, e.g. parallel decode units · CPC title