Processing System, Related Integrated Circuit and Method

Patent metadata

Field	Value
Publication number	US-2019272211-A1
Application number	US-201916289425-A
Country	US
Kind code	A1
Filing date	Feb 28, 2019
Priority date	Mar 2, 2018
Publication date	Sep 5, 2019
Grant date	—

Abstract

A processing system includes a processing unit configured to be connected to a memory with error detection and/or correction. The processing unit generates at least one read request for reading data from the memory, the read request including an address signal identifying an address of a given memory area in the memory. The processing system includes an error handling circuit connected to the memory for receiving an error signal containing an error code indicating whether the data read from the memory contains errors. The error handling circuit includes a hardware circuit configured to set a first error signal to the error code of the error signal when the address indicated by the address signal belongs to a first address range and to set a second error signal to the error code of the error signal when the address indicated by the address signal belongs to a second address range.

First claim

What is claimed is:

1 . A processing system, comprising:
a processing unit configured to generate at least one read request for reading data from a memory with error detection and/or correction, the read request comprising an address signal identifying an address of a given memory area in the memory; and an error handling circuit configured to be connected to the memory and to receive an error signal from the memory, wherein the error signal comprises an error code indicating whether the data read from the memory contains errors, wherein the error handling circuit comprises a hardware circuit configured to:
determine whether the address indicated by the address signal belongs to a first address range;
set an error code of a first error signal to the error code of the error signal when the address indicated by the address signal belongs to the first address range;
determine whether the address indicated by the address signal belongs to a second address range; and
set an error code of a second error signal to the error code of the error signal when the address indicated by the address signal belongs to the second address range.

2 . The processing system according to claim 1 , wherein the hardware circuit comprises a first combinational logic circuit configured to set a first enable signal to:
a first logic value when the address indicated by the address signal belongs to the first address range; and a second logic value when the address indicated by the address signal does not belong to the first address range.

3 . The processing system according to claim 2 , wherein the hardware circuit further comprises a second combinational logic circuit configured to set a second enable signal to:
the first logic value when the address indicated by the address signal belongs to the second address range; and the second logic value when the address indicated by the address signal does not belong to the second address range.

4 . The processing system according to claim 3 , wherein the hardware circuit further comprises a third combinational logic circuit configured to:
set the error code of the first error signal to the error code of the error signal when the first enable signal has the first logic value; and set the error code of the second error signal to the error code of the error signal when the second enable signal has the first logic value.

5 . The processing system according to claim 1 , wherein at least one of the first address range or the second address range is programmable.

6 . The processing system according to claim 1 , wherein the error handling circuit comprises:
a register configured to store the error code of the error signal and to provide the error code to the hardware circuit for generating the first error signal and the second error signal.

7 . The processing system according to claim 6 , wherein the register is further configured to store the error code of the first error signal and the error code of the second error signal.

8 . The processing system according to claim 1 , further comprising an interrupt generator circuit configured to generate one or more interrupt signals when the error code of the first error signal corresponds to one or more first reference values.

9 . The processing system according to claim 8 , wherein the interrupt generator circuit is further configured to generate the one or more interrupt signals when the error code of the second error signal corresponds to one or more second reference values.

10 . The processing system according to claim 9 , wherein at least one of the one or more first reference values or the one or more second reference values is programmable.

11 . The processing system according to claim 9 , wherein at least one of the one or more interrupt signals, the first error signal or the second error signal is provided to the processing unit.

12 . The processing system according to claim 9 , wherein the processing system comprises a communication interface, and wherein at least one of the one or more interrupt signals, the first error signal or the second error signal is provided directly to the communication interface.

13 . The processing system according to claim 9 , wherein the processing system comprises a pin, and wherein at least one of the one or more interrupt signals, the first error signal or the second error signal is provided directly to the pin.

14 . The processing system according to claim 1 , wherein the error signal comprises a plurality of bits, and wherein the error code of the error signal indicates at least one of:
no error having occurred during a reading operation of the data; an error having occurred during the reading operation of the data and that the error was corrected; or an error having occurred during the reading operation of the data and that the error was not corrected.

15 . The processing system according to claim 1 , wherein the processing unit is a micro-processor configured to be programmed via software instructions.

16 . The processing system according claim 1 , further comprising the memory with error detection and/or correction.

17 . The processing system according to claim 1 , wherein the memory with error detection and/or correction comprises at least one of a non-volatile memory arranged to store firmware for the processing unit or a random-access memory arranged to store temporary results of processing by the processing unit.

18 . A method of operating a processing system, the method comprising:
storing data into a memory with error detection and/or correction; generating, via a processing unit of the processing system, at least one read request for reading data from a given address of the memory with error detection and/or correction; and generating, via an error handling circuit of the processing system, a first error signal and a second error signal as a function of the given address and an error signal received from the memory with error detection and/or correction.

19 . The method according to claim 18 , wherein the error handling circuit comprises a hardware circuit, and wherein the method further comprises:
determining, by the hardware circuit, whether the given address belongs to a first address range; setting, by the hardware circuit, an error code of the first error signal to an error code of the error signal when the given address belongs to the first address range; determining, by the hardware circuit, whether the given address belongs to a second address range; and setting, by the hardware circuit, an error code of the second error signal to the error code of the error signal when the given address belongs to the second address range.

20 . The method according to claim 19 , wherein at least one of the first address range or the second address range is programmable.

Assignees

• Stmicroelectronics Application Gmbh

Inventors

• Colombo Roberto

Classifications

• G06F11/0727

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/0751

  Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06) · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title