Power semiconductor device with an auxiliary gate structure

Patent metadata

Field	Value
Publication number	US-2019267482-A1
Application number	US-201916405619-A
Country	US
Kind code	A1
Filing date	May 7, 2019
Priority date	Jul 14, 2017
Publication date	Aug 29, 2019
Grant date	—

Abstract

The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal. In other embodiments a pull-down network for the switching-off of the high threshold voltage GaN transistor is formed by additional auxiliary low-voltage GaN transistors and resistive elements connected in parallel or in series with the low-voltage auxiliary GaN transistor.

First claim

1 . A III-nitride power semiconductor based heterojunction device, comprising:
an active heterojunction transistor formed on a substrate, the active heterojunction transistor comprising:
a first III-nitride semiconductor region comprising a first heterojunction comprising an active two dimensional carrier gas of second conductivity type;
a first terminal operatively connected to the III-nitride semiconductor region;
a second terminal laterally spaced from the first terminal and operatively connected to the III-nitride semiconductor region;
an active gate region formed over the III-nitride semiconductor region, the active gate region being formed between the first terminal and the second terminal;
an auxiliary heterojunction transistor formed on the said substrate or a further substrate, the auxiliary heterojunction transistor comprising:
a second III-nitride semiconductor region comprising a second heterojunction comprising an auxiliary two dimensional carrier gas of second conductivity type;
a first additional terminal operatively connected to the second III-nitride semiconductor region;
a second additional terminal laterally spaced from the first additional terminal and operatively connected to the second III-nitride semiconductor region;
an auxiliary gate region formed over the second III-nitride semiconductor region, the auxiliary gate region being formed between the first additional terminal and the second additional terminal;
wherein the first additional terminal is operatively connected with the auxiliary gate region, and wherein the second additional terminal is operatively connected with the active gate region; and wherein the auxiliary heterojunction transistor is a first auxiliary heterojunction transistor, and wherein the heterojunction power device further comprises a second auxiliary heterojunction transistor which is operatively connected in parallel with the first auxiliary transistor, and wherein the first additional terminal of the first auxiliary heterojunction transistor is operatively connected to a source terminal of the second auxiliary heterojunction transistor, and the second additional terminal of the first auxiliary heterojunction transistor is operatively connected to a drain terminal of the second auxiliary heterojunction transistor.

2 . A depletion mode III-nitride semiconductor based heterojunction device, comprising:
a substrate; a III-nitride semiconductor region formed over the substrate, wherein the III-nitride semiconductor region comprises a heterojunction comprising at least one two-dimensional carrier gas of second conductivity type; a first terminal operatively connected to the III-nitride semiconductor region; a second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the III-nitride semiconductor region; at least two highly doped semiconductor regions of a first conductivity type formed over the III-nitride semiconductor region, the at least two highly doped semiconductor regions being formed between the first terminal and the second terminal; and an active gate region formed over the at least two highly doped semiconductor regions; wherein the at least two highly doped semiconductor regions are spaced from each other in a second dimension and wherein the second dimension is perpendicular to the first dimension.

3 . A heterojunction power device according to claim 1 , further comprising a first resistor located in series with the second auxiliary transistor between a gate terminal and the drain terminal of the second auxiliary transistor.

4 . A heterojunction power device according to claim 3 , further comprising a second resistor operatively connected between the drain terminal of the second auxiliary transistor and the second terminal of the active (high voltage) transistor.

5 . A heterojunction power device according to claim 1 , further comprising a third auxiliary transistor located in series with the second auxiliary transistor between the gate and drain terminals of the second auxiliary transistor.

6 . A heterojunction power device according to claim 5 wherein a gate terminal of the third auxiliary transistor is connected to a source terminal or a drain terminal of the third auxiliary transistor.

7 . A heterojunction power device according to claim 5 , wherein the third auxiliary transistor is configured to reduce active gate capacitance discharge time during turn-off of the heterojunction power device by increasing potential of the gate terminal of the second auxiliary transistor compared to the drain terminal of the second auxiliary transistor.

8 . A heterojunction power device according to claim 5 , wherein the third auxiliary transistor is a depletion mode transistor according to a depletion mode III-nitride semiconductor based heterojunction device, comprising:
a substrate; a III-nitride semiconductor region formed over the substrate, wherein the III-nitride semiconductor region comprises a heterojunction comprising at least one two-dimensional carrier gas of second conductivity type; a first terminal operatively connected to the III-nitride semiconductor region; a second terminal laterally spaced from the first terminal in a first dimension and operatively connected to the III-nitride semiconductor region; at least two highly doped semiconductor regions of a first conductivity type formed over the III-nitride semiconductor region, the at least two highly doped semiconductor regions being formed between the first terminal and the second terminal; and an active gate region formed over the at least two highly doped semiconductor regions; wherein the at least two highly doped semiconductor regions are spaced from each other in a second dimension and wherein the second dimension is perpendicular to the first dimension.

9 . A heterojunction power device according to claim 5 , further comprising an additional resistor operatively connected between the drain terminal of the second auxiliary transistor and the second terminal of the active (high voltage) transistor.

10 . A heterojunction power device according to claim 1 , further comprising a voltage limiting circuit comprising at least two resistors forming a potential divider and an actively switched low voltage enhancement mode transistor.

11 . A heterojunction power device according to claim 10 , wherein a drain terminal of the actively switched low voltage enhancement mode transistor is connected with the gate terminal of the active high voltage transistor and a source terminal of the actively switched low voltage enhancement mode transistor is connected with the source terminal of the active high voltage transistor.

12 . A heterojunction power device according to claim 10 , wherein the potential divider is operatively connected between the first additional terminal of the first auxiliary heterojunction transistor and the second terminal of the active high voltage transistor.

13 . A heterojunction power device according to claim 10 , wherein a mid-point of the potential divider is operatively connected to the gate terminal of the low voltage enhancement mode transistor.

14 . A heterojunction power device according to claim 1 , further comprising a voltage limiting circuit comprising at least two resistors forming a potential divider and a low voltage depletion mode transistor.

15 . A heterojunction power device according to claim 1 , further comprising an over-current protection circuit comprising a current sensing resistor and an actively switched low voltage enhancement mode transistor.

16 . A heterojun

Assignees

• Cambridge Entpr Ltd

Inventors

• Udrea Florin
• Efthymiou Loizos
• Longobardi Giorgia
• Arnold Martin

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/00

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title

• H10W10/01

  Manufacture or treatment · CPC title

• H01L27/0629

  Electricity · mapped topic