High-speed interface apparatus and deskew method thereof

Patent metadata

Field	Value
Publication number	US-2019260569-A1
Application number	US-201916394625-A
Country	US
Kind code	A1
Filing date	Apr 25, 2019
Priority date	Feb 13, 2014
Publication date	Aug 22, 2019
Grant date	—

Abstract

A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.

First claim

What is claimed is:

1 . A transmitter for communicating with a receiver, the transmitter comprising:
a first buffer connected to the receiver through a first channel; a second buffer connected to the receiver through a second channel; and a third buffer connected to the receiver through a third channel, wherein the transmitter is configured to: transmit test data to the receiver using the first to third buffers; transmit a synchronous code to the receiver using the first to third buffers after transmitting the test data; and transmit normal data to the receiver using the first to third buffers after transmitting the synchronous code.

2 . The transmitter of claim 1 , further comprising:
a normal data processor configured to receive parallel data and convert the parallel data to serial data which is the normal data; a test data generator configured to generate the test data and provide the test data to the first to third buffers; and a synchronous code generator configured to generate the synchronous code and provide the synchronous code to the first to third buffers.

3 . The transmitter of claim 1 , further configured to:
transmit a first synchronous code, which is different from the synchronous code, to the receiver using the first to third buffer, before transmitting the test data.

4 . The transmitter of claim 3 , further comprising:
a deskew synchronous code generator configured to generate the first synchronous code and provide the first synchronous code to the first to third buffers.

5 . The transmitter of claim 3 , further configured to transmit the first synchronous code during a power-up sequence.

6 . The transmitter of claim 1 , wherein the test data has a pattern in which 0 and 1 alternate.

7 . The transmitter of claim 1 , wherein, during at least part of a period in which the test data is transmitted, data output from one buffer among the first to third buffers and data output from other buffer among the first to third buffers are different from each other.

8 . The transmitter of claim 1 , further configured to:
drive the first to third buffers in a first mode during a first period, and drive the first to third buffers in a second mode for transmitting the test data during a second period after the first period.

9 . The transmitter of claim 8 , wherein a level corresponding to a first level from among first levels of first signals output from the first to third buffers during the first period, and a level corresponding to the first level from among second levels of second signals output from the first to third buffers during the second period are different from each other.

10 . The transmitter of claim 8 , wherein first levels of first signals output from the first to third buffers during the first period correspond to first and second logic values,
second levels of second signals output from the first to third buffers during the second period correspond to the first and second logic values, and a difference between the second levels is smaller than a difference between the first levels.

11 . The transmitter of claim 8 , further configured to transmit the test data after the second period.

12 . A transmitter for communicating with a receiver, the transmitter configured to:
switch from a first mode to a second mode which is a high speed mode compared with the first mode; transmit test data to the receiver after switching to the second mode; transmit a synchronous code to the receiver after transmitting the test data; and transmit normal data to the receiver after transmitting the synchronous code.

13 . The transmitter of claim 12 , comprising:
first to third buffers respectively connected to the receiver through first to third channels, wherein the first to third buffers are configured to transmit the test data, the synchronous code, and the normal data to the receiver.

14 . The transmitter of claim 13 , wherein, during at least part of a period in which the first to third buffers operate in the second mode, levels of signals of the first to third buffers are fixed.

15 . The transmitter of claim 12 , further configured to switch from the second mode to the first mode again after transmitting the normal data.

16 . The transmitter of claim 15 , further configured to:
switch from the first mode to the second mode again; transmit the test data to the receiver after switching to the second mode again; transmit the synchronous code to the receiver after transmitting the test data; and transmit new normal data to the receiver after transmitting the synchronous code.

17 . The transmitter of claim 12 , wherein the test data is predetermined.

18 . A transmitter for communicating with a receiver, the transmitter configured to:
switch from a first mode to a second mode which is a high speed mode compared with the first mode; transmit a first synchronous code to the receiver after switching to the second mode; transmit test data to the receiver after transmitting the first synchronous code; transmit a second synchronous code to the receiver after transmitting the test data; and transmit normal data to the receiver after transmitting the second synchronous code.

19 . The transmitter of claim 18 , comprising:
first to third buffers respectively connected to the receiver through first to third channels, wherein the first to third buffers are configured to transmit the first synchronous code, the test data, the second synchronous code, and the normal data to the receiver.

20 . The transmitter of claim 18 , wherein the first synchronous code and the second synchronous code are different from each other.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Han Soo
• Kim Sung Jun
• Kim Chae Ryung
• Park Dong Uk
• Chung Youn Woong
• Choi Jung Myung
• Lim Han Kyul
• Cha Gyeong Han

Classifications

• H04L7/0016

  correction of synchronization errors · CPC title

• H03K2005/00058

  controlled by a digital setting · CPC title

• H03K5/131

  Digitally controlled · CPC title

• H04L25/14 Primary

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

• G01R31/31725

  Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937) · CPC title