Controlling output voltage for power converter

Patent metadata

Field	Value
Publication number	US-2019260296-A1
Application number	US-201916402833-A
Country	US
Kind code	A1
Filing date	May 3, 2019
Priority date	Jun 2, 2016
Publication date	Aug 22, 2019
Grant date	—

Abstract

A circuit includes an overshoot-and-undershoot (OU) signal generator generating a signal indicating detection of an overshoot or an undershoot of an output signal of the power converter. The circuit further includes a feedback signal modulator receiving a first feedback signal and the signal indicating detection of the overshoot or the undershoot and generating a second feedback signal in response to the first feedback signal and the signal indicating detection of the overshoot or the undershoot. The feedback signal modulator generates the second feedback signal that is different from the first feedback signal during a predetermined time interval after the signal indicating detection of the overshoot or the undershoot has been asserted.

First claim

What is claimed is:

1 . A circuit for controlling a power converter comprising:
an overshoot-and-undershoot (OU) signal generator configured to generate a signal indicating detection of an overshoot or an undershoot of an output signal of the power converter; and a feedback signal modulator configured to receive a first feedback signal and the signal indicating detection of the overshoot or the undershoot and to generate a second feedback signal in response to the first feedback signal and the signal indicating detection of the overshoot or the undershoot, wherein the feedback signal modulator generates the second feedback signal that is different from the first feedback signal during a predetermined time interval after the signal indicating detection of the overshoot or the undershoot has been asserted.

2 . The circuit of claim 1 , wherein the signal is an overshoot signal indicating detection of the overshoot, and the OU signal generator generates the overshoot signal based on a tracking signal, the tracking signal indicating the output signal of the power converter.

3 . The circuit of claim 2 , wherein the OU signal generator includes:
a comparator comparing a value of the tracking signal to a value of an overshoot enable threshold signal to generate a comparison signal; and a delay circuit delaying the comparison signal with a given delay amount to generate a delayed version of the comparison signal.

4 . The circuit of claim 3 , wherein the OU signal generator further includes a flip-flop generating the overshoot signal having a pulse width that corresponds to the given delay amount of the delay circuit.

5 . The circuit of claim 1 , wherein the signal is an undershoot signal indicating detection of the undershoot, and the OU signal generator generates the undershoot signal based on a tracking signal, the tracking signal indicating the output signal of the power converter.

6 . The circuit of claim 5 , wherein the OU signal generator includes:
a comparator comparing a value of the tracking signal to a value of an undershoot enable threshold signal to generate a comparison signal; and a delay circuit delaying the comparison signal with a given delay amount to generate a delayed version of the comparison signal.

7 . The circuit of claim 6 , wherein the OU signal generator further includes a flip-flop generating the undershoot signal having a pulse width that corresponds to the given delay amount of the delay circuit.

8 . The circuit of claim 2 , wherein the OU signal generator further generates an undershoot signal indicating detection of the undershoot based on the tracking signal to output the undershoot signal to the feedback signal modulator, and
wherein the feedback signal modulator includes: a first node receiving the first feedback signal; a second node generating the second feedback signal; a logic gate performing a logical operation on the overshoot signal and the undershoot signal; and a first switching device coupling the first node to the second node in response to an output signal of the logic gate.

9 . The circuit of claim 8 , wherein the feedback signal modulator further includes:
a second switching device coupling a power supply voltage to the second node in response to the undershoot signal; and a third switching device coupling the second node to a ground in response to the overshoot signal.

10 . The circuit of claim 1 , wherein the OU signal generator includes a delay circuit configured to de-assert the signal indicating detection of the overshoot or the undershoot, the predetermined time interval corresponding to a delay amount of the delay circuit.

11 . The circuit of claim 1 , further comprising a modulation controller configured to generate a modulation signal in response to the second feedback signal,
wherein the modulation controller adjusts one or both of an on-time duration and a switching frequency of the modulation signal in response to the second feedback signal.

12 . A power converter comprising:
a first side circuit generating an input signal; and a second side circuit generating an output signal in response to the input signal, wherein the first side circuit includes:
a switching device; and
a first side controller configured to generate a signal indicating detection of an overshoot or an undershoot of the output signal, generate a first feedback signal in response to a tracking signal, the tracking signal indicating the output signal, and generate a second feedback signal in response to the first feedback signal and the signal indicating detection of the overshoot or the undershoot, and
wherein the first side controller generates the second feedback signal that is different from the first feedback signal during a predetermined time interval after the signal indicating detection of the overshoot or the undershoot has been asserted.

13 . The power converter of claim 12 , wherein the first side controller generates a modulation signal and adjusts one or both of an on-time duration and a switching frequency of the modulation signal in response to the second feedback signal.

14 . The power converter of claim 12 , wherein the first side controller includes a delay circuit configured to de-assert the signal indicating detection of the overshoot or the undershoot, the predetermined time interval corresponding to a delay amount of the delay circuit.

15 . A method for controlling a power converter, the method comprising:
generating a signal indicating detection of an overshoot or an undershoot of an output signal of the power converter; receiving a first feedback signal at a first node; generating a second feedback signal at a second node in response to the first feedback signal and the signal indicating detection of the overshoot or the undershoot; and decoupling the second node from the first node to generate the second feedback signal that is different from the first feedback signal during a predetermined time interval after the signal indicating detection of the overshoot or the undershoot has been asserted.

16 . The method of claim 15 , wherein the signal is an overshoot signal indicating detection of the overshoot, the method further comprising generating the overshoot signal based on a tracking signal, the tracking signal indicating the output signal of the power converter.

17 . The method of claim 16 , further comprising:
comparing a value of the tracking signal to a value of an overshoot enable threshold signal to generate a comparison signal; and delaying the comparison signal with a given delay amount to generate a delayed version of the comparison signal.

18 . The method of claim 15 , wherein the signal is an undershoot signal indicating detection of the undershoot, the method further comprising generating the undershoot signal based on a tracking signal, the tracking signal indicating the output signal of the power converter.

19 . The method of claim 18 , further comprising:
comparing a value of the tracking signal to a value of an undershoot enable threshold signal to generate a comparison signal; and delaying the comparison signal with a given delay amount to generate a delayed version of the comparison signal.

20 . The method of claim 15 , further comprising de-asserting the signal indicating detection of the overshoot or the undershoot by a delay circuit,
wherein the predetermined time interval corresponds to a delay amount of the delay circuit.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Eum Hyun-Chul
• Kim Tae-Sung
• Kim Young-Jong

Classifications

• H05B45/48

  having LEDs organised in strings and incorporating parallel shunting devices · CPC title

• H05B45/44

  with an active control inside an LED matrix · CPC title

• H05B45/37

  Converter circuits · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02H7/1213 Primary

  for DC-DC converters · CPC title