Write assist

Patent metadata

Field	Value
Publication number	US-2019244658-A1
Application number	US-201815891619-A
Country	US
Kind code	A1
Filing date	Feb 8, 2018
Priority date	Feb 8, 2018
Publication date	Aug 8, 2019
Grant date	—

Abstract

A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.

First claim

What is claimed is:

1 . A circuit, comprising:
a core comprising a memory array, the memory array comprising memory cells having bitlines, the memory array being arranged in columns, wherein the core includes a metallization layer comprising connections to the memory array, and wherein the metallization layer is devoid of memory cells; digit lines connected to the bitlines of a column of the memory array; a write driver connected to the digit lines; and a write assist circuit connected to the write driver, wherein the write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations, and wherein a wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.

2 . The circuit according to claim 1 , wherein the digit lines are connected to the bitlines through column muxing NMOS transistors.

3 . The circuit according to claim 1 , the write assist circuit further comprising:
a true boost signal connected to a true digit line, a complement boost signal connected to a complement digit line, a first capacitor connected to the true boost signal, and a second capacitor connected to the complement boost signal, the first capacitor being different from the second capacitor.

4 . The circuit according to claim 3 , wherein a single clock signal is used and the write driver predischarges the first capacitor and the second capacitor prior to providing write assist.

5 . The circuit according to claim 3 , wherein the write assist circuit further comprises a pair of OR gates connected to each pair of digit lines to provide a boost voltage to the digit lines during write operations, and pairs of precharge transistors connected to each pair of digit lines maintaining a voltage on the digit lines prior to write operations.

6 . The circuit according to claim 5 , wherein boosting of bitlines is based on feedback from the bitlines to each of the OR gates.

7 . The circuit according to claim 3 , wherein the write assist circuit further comprises a pair of NAND gates connected to each pair of digit lines to provide a boost voltage to the digit lines during write operations, and pairs of precharge transistors connected to each pair of digit lines maintaining a voltage on the digit lines prior to write operations.

8 . The circuit according to claim 7 , wherein boosting of digit lines is based on feedback from the digit lines to each of the NAND gates.

9 . A device, comprising:
a core comprising a memory array, the memory array comprising memory cells having bitlines, the memory array being arranged in columns, wherein the core includes a metallization layer comprising connections to the memory array, and wherein the metallization layer is devoid of memory cells; digit lines connected to the bitlines of a column of the memory array; a write driver connected from a first digit line and a second digit line to each of the memory cells of the memory array, the write driver comprising:
a first transistor connected from the first digit line to ground, and
a second transistor connected from the second digit line to ground; and
a write assist circuit connected to the write driver, wherein a wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver, the write assist circuit comprising:
a first precharge transistor connected to the first digit line, the first precharge transistor maintaining a first voltage on the first digit line prior to write operations,
a second precharge transistor connected to the second digit line, the second precharge transistor maintaining a second voltage on the second digit line prior to write operations,
a first boost signal connected to the first digit line, the first boost signal providing a first boost voltage to the first digit line during write operations, and
a second boost signal connected to the second digit line, the second boost signal providing a second boost voltage to the second digit line during write operations.

10 . The device according to claim 9 , wherein the digit lines are connected to the bitlines through column muxing NMOS transistors.

11 . The device according to claim 9 , wherein
the first boost signal comprises a true boost signal connected to a true digit line, and the second boost signal comprises a complement boost signal connected to a complement digit line,
the write assist circuit further comprising:
a first capacitor connected to the true boost signal, and
a second capacitor connected to the complement boost signal, the first capacitor being different from the second capacitor.

12 . The device according to claim 11 , wherein a single clock signal is used and the write driver predischarges the first capacitor and the second capacitor prior to providing write assist.

13 . The device according to claim 11 , the write assist circuit further comprising:
a first logic gate connected to the first digit line providing a boost voltage to the first digit line during write operations, and a second logic gate connected to the second digit line providing a boost voltage to the second digit line during write operations, the first logic gate and second logic gate being the same type of logic gate.

14 . The device according to claim 13 , wherein boosting of the digit lines is based on feedback from the digit lines to the first logic gate and the second logic gate.

15 . A method, comprising:
providing a core comprising a memory array, the memory array comprising memory cells having bitlines, the memory array being arranged in columns, the core further comprising a metallization layer comprising connections to the memory array, and wherein the metallization layer is devoid of memory cells; connecting a write driver to the memory array using digit lines connected to the bitlines of a column of the memory array; and connecting a write assist circuit to the write driver using a wire bridge located in a metallization layer of the core.

16 . The method according to claim 15 , wherein the digit lines are connected to the bitlines through column muxing NMOS transistors.

17 . The method according to claim 15 , the write assist circuit further comprising:
a first precharge transistor connected to a first digit line, the first precharge transistor maintaining a first voltage on the first digit line prior to write operations, a second precharge transistor connected to a second digit line, the second precharge transistor maintaining a second voltage on the second digit line prior to write operations, a first boost signal connected to the first digit line, the first boost signal providing a first boost voltage to the first digit line during write operations, and a second boost signal connected to the second digit line, the second boost signal providing a second boost voltage to the second digit line during write operations.

18 . The method according to claim 17 , wherein a single clock signal is used, and the write driver removes the first voltage and the second voltage prior to providing the first boost signal and the second boost signal.

19 . The method according to claim 17 , wherein
the first boost signal comprises a true boost signal connected to a true digit line, and the second boost signal comprises a complement boost signal connected to a complement digit line,
the write assist circuit further comprising:
a first capacitor connected to the tru

Assignees

• Globalfoundries Inc

Inventors

• Dhani Reddy Sreenivasula Reddy
• Chidambaran Sreejith
• Jose Binu
• Bringivijayaraghavan Venkatraghavan

Classifications

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C7/12 Primary

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C11/412 Primary

  using field-effect transistors only · CPC title