Configurable bus

Patent metadata

Field	Value
Publication number	US-2019227818-A1
Application number	US-201916374907-A
Country	US
Kind code	A1
Filing date	Apr 4, 2019
Priority date	Jan 30, 2006
Publication date	Jul 25, 2019
Grant date	—

Abstract

A device includes an analog block array, a first analog bus segment coupled to the analog block array, a second analog bus segment coupled to the analog block array, and a third analog bus segment coupled to the analog block array. The device also includes a first I/O pin selectively couplable to the first analog bus segment, a second I/O pin selectively couplable to the second analog bus segment, and a third I/O pin selectively couplable to the third analog bus segment. A first switch is configured to selectively propagate a first analog signal on the first analog bus segment to the second analog bus segment, and a second switch is configured to selectively propagate a second analog signal on the first analog bus segment to the third analog bus segment. In a first mode of operation, the first and second switches are open. In a second mode of operation, the first switch is closed. In a third mode of operation, the second switch is closed.

First claim

What is claimed is:

1 . A device, comprising:
an analog block array; a first analog bus segment coupled to the analog block array; a second analog bus segment coupled to the analog block array; a third analog bus segment coupled to the analog block array; a first I/O pin selectively couplable to the first analog bus segment; a second I/O pin selectively couplable to the second analog bus segment; a third I/O pin selectively couplable to the third analog bus segment; a first switch configured to selectively propagate a first analog signal on the first analog bus segment to the second analog bus segment; and a second switch configured to selectively propagate a second analog signal on the first analog bus segment to the third analog bus segment; wherein in a first mode of operation, the first and second switches are open, in a second mode of operation, the first switch is closed, and in a third mode of operation, the second switch is closed.

2 . The device of claim 1 , further comprising a fourth analog bus segment, wherein:
in the second mode of operation, the fourth analog bus segment is connected to the third analog bus segment and is disconnected from the first analog bus segment and the second analog bus segment, and in the third mode of operation, the fourth analog bus segment is connected to the second analog bus segment and is disconnected from the first analog bus segment and the third analog bus segment.

3 . The device of claim 2 , wherein the first and second analog bus segments are each located nearer to a first edge of an integrated circuit chip on which the device resides than either of the third and fourth analog bus segments, and wherein the third and fourth analog bus segments are each located nearer to a second edge of the integrated circuit chip opposite the first edge than either of the first and second analog bus segments.

4 . The device of claim 1 , wherein each of the first I/O pin, the second I/O pin, and the third I/O pin is selectively connectable to no more than one of the first analog bus segment, the second analog bus segment, and the third analog bus segment.

5 . The device of claim 1 , wherein the analog block array comprises reconfigurable analog circuitry.

6 . The device of claim 1 , further comprising a set of capacitance sensing circuits each connected to one of the first analog bus segment, the second analog bus segment, and the third analog bus segment, and each configured to measure an external capacitance connected to one of the first I/O pin, the second I/O pin, and the third I/O pin.

7 . The device of claim 6 , wherein each capacitance sensing circuit in the set of capacitance sensing circuits is configured to transmit a trigger signal to a microprocessor in response to a change in the external capacitance.

8 . The device of claim 1 , further comprising a set of digital-to-analog converters (DACs), wherein each DAC of the set of DACs is configured to, based on input from a microprocessor, inject a current into one of the first analog bus segment, the second analog bus segment, and the third analog bus segment.

9 . The device of claim 1 , further comprising a switch register coupled with a microprocessor, wherein the switch register is configured to control the first switch and the second switch based on data written to the switch register by the microprocessor.

10 . The device of claim 1 , further comprising a set of digital-to-analog converters (DACs), wherein each DAC of the set of DACs is configured to, based on input from a microprocessor, inject a current into one of the first analog bus segment, the second analog bus segment, and the third analog bus segment.

11 . The device of claim 1 , further comprising a system bus configured to couple the analog block array with a microprocessor and with a switch register for controlling the first and second switches, wherein the analog block array and the switch register reside on an integrated circuit with the microprocessor.

12 . A system, comprising:
a microprocessor; an analog block array; a first analog bus segment coupled to the analog block array; a second analog bus segment coupled to the analog block array; a third analog bus segment coupled to the analog block array; a first I/O pin selectively couplable to the first analog bus segment; a second I/O pin selectively couplable to the second analog bus segment; a third I/O pin selectively couplable to the third analog bus segment; a first switch configured to selectively propagate a first analog signal on the first analog bus segment to the second analog bus segment; and a second switch configured to selectively propagate a second analog signal on the first analog bus segment to the third analog bus segment; wherein in a first mode of operation, the first and second switches are open, in a second mode of operation, the first switch is closed, and in a third mode of operation, the second switch is closed.

13 . The system of claim 12 , further comprising a switch register coupled with the microprocessor, wherein the switch register is configured to control the first switch and the second switch based on data written to the switch register by the microprocessor.

14 . The system of claim 12 , further comprising a set of capacitance sensing circuits each connected to one of the first analog bus segment, the second analog bus segment, and the third analog bus segment, and each configured to transmit a trigger signal to the microprocessor in response to a change in an external capacitance.

15 . The system of claim 12 , further comprising a set of capacitance sensing circuits each connected to one of the first analog bus segment, the second analog bus segment, and the third analog bus segment, and each configured to measure an external capacitance connected to one of the first I/O pin, the second I/O pin, and the third I/O pin and indicate to the microprocessor a change in the external capacitance.

16 . The system of claim 12 , further comprising a set of digital-to-analog converters (DACs), wherein each DAC of the set of DACs is configured to, based on input from the microprocessor, inject a current into one of the first analog bus segment, the second analog bus segment, and the third analog bus segment.

17 . The system of claim 12 , wherein the analog block array comprises reconfigurable analog circuitry.

18 . The system of claim 12 , further comprising a system bus configured to couple the microcontroller with the analog block array and with a switch register for controlling the first switch and the second switch, wherein the analog block array and the switch register reside on an integrated circuit with the microcontroller.

19 . The system of claim 12 , further comprising a fourth analog bus segment, wherein:
in the second mode of operation, the fourth analog bus segment is connected to the third analog bus segment and is disconnected from the first analog bus segment and the second analog bus segment, and in the third mode of operation, the fourth analog bus segment is connected to the second analog bus segment and is disconnected from the first analog bus segment and the third analog bus segment.

20 . The system of claim 19 , wherein the first and second analog bus segments are each routed along a first portion of a perimeter of an integrated circuit chip on which the microprocessor and the analog block array reside, and wherein the third and fourth analog bus segments are each routed along a second portion of the

Assignees

• Cypress Semiconductor Corp

Inventors

• Kutz Harold M
• Snyder Warren S
• Williams Timothy John
• Thiagarajan Eashwar

Classifications

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F9/44505 Primary

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F15/7817

  Specially adapted for signal processing, e.g. Harvard architectures · CPC title