Photolithographic method for fabricating dense pillar arrays using spacers as a pattern

Patent metadata

Field	Value
Publication number	US-2019207101-A1
Application number	US-201715857499-A
Country	US
Kind code	A1
Filing date	Dec 28, 2017
Priority date	Dec 28, 2017
Publication date	Jul 4, 2019
Grant date	—

Abstract

A method for fabricating an array of pillars. The method includes fabricating a plurality of lines of photoresist on a hard mask stack and depositing a spacer film on top of the plurality of lines of photoresist. The method further includes etching the spacer film to remove the spacer film from the top of the plurality of lines of photoresist and stripping the plurality of lines of photoresist to leave behind to spacer lines for each resist line. The method concludes with etching the spacer lines and the hard mask stack to yield an array of pillars.

First claim

What is claimed is:

1 . A method for fabricating an array of pillars, the method comprising:
fabricating a plurality of lines of photoresist on a hard mask stack; depositing a spacer film on top of the plurality of lines of photoresist; etching the spacer film to remove the spacer film from the top of the plurality of lines of photoresist; stripping the plurality of lines of photoresist to leave behind to spacer lines for each resist line; etching the spacer lines and the hard mask stack to yield an array of pillars.

2 . The method of claim 1 , wherein the hard mask stack comprises a multilayer hard mask stack.

3 . The method of claim 2 , wherein the multilayer hard mask stack includes a bottom antireflective coating layer (BARC).

4 . The method of claim 1 , wherein reactive ion etching (REI) etches the hard mask stack to form hard mask pillars on top of an MTJ metal stack.

5 . The method of claim 1 , wherein the hard mask stack comprises a multilayer hard mask stack comprising a bottom antireflective coating (BARC) layer, a first hard mask layer, and a second hard mask layer.

6 . The method of claim 5 , wherein the first hard mask layer comprises tantalum nitride and the second hard mask layer comprises silicon oxide.

7 . The method of claim 1 , wherein wafers produced using photolithography patterning proceed through a subsequent MTJ fabrication process.

8 . A method for producing pillar arrays in a wafer fabrication process, the method comprising:
fabricating a plurality of lines of photoresist on a hard mask stack, wherein the hard mask stack comprises a multilayer hard mask stack; depositing a spacer film on top of the plurality of lines of photoresist; etching the spacer film to remove the spacer film from the top of the plurality of lines of photoresist; stripping the plurality of lines of photoresist to leave behind to spacer lines for each resist line; etching the spacer lines and the hard mask stack to yield an array of pillars.

9 . The method of claim 8 , wherein a plurality of etches are implemented to yield the array of pillars.

10 . The method of claim 8 wherein the multilayer hard mask stack includes a bottom antireflective coating layer (BARC).

11 . The method of claim 8 , wherein reactive ion etching (REI) etches the hard mask stack to form hard mask pillars on top of an MTJ metal stack.

12 . The method of claim 8 , wherein the hard mask stack comprises a multilayer hard mask stack comprising a bottom antireflective coating (BARC) layer, a first hard mask layer, and a second hard mask layer.

13 . The method of claim 12 , wherein the first hard mask layer comprises tantalum nitride and the second hard mask layer comprises silicon oxide.

14 . The method of claim 8 , wherein wafers produced using photolithography patterning proceed through a subsequent MTJ fabrication process.

15 . A method for manufacturing an MRAM device, the method comprising:
fabricating a plurality of lines of photoresist on a hard mask stack; depositing a spacer film on top of the plurality of lines of photoresist; etching the spacer film to remove the spacer film from the top of the plurality of lines of photoresist; stripping the plurality of lines of photoresist to leave behind to spacer lines for each resist line; etching the spacer lines and the hard mask stack to yield an array of pillars.

16 . The method of claim 15 , wherein the hard mask stack comprises a multilayer hard mask stack.

17 . The method of claim 16 , wherein the multilayer hard mask stack includes a bottom antireflective coating layer (BARC).

18 . The method of claim 15 , wherein reactive ion etching (REI) etches the hard mask stack to form hard mask pillars on top of an MTJ metal stack.

19 . The method of claim 15 , wherein the hard mask stack comprises a multilayer hard mask stack comprising a bottom antireflective coating (BARC) layer, a first hard mask layer, and a second hard mask layer.

20 . The method of claim 15 , wherein the first hard mask layer comprises tantalum nitride and the second hard mask layer comprises silicon oxide.

Assignees

• Spin Transfer Tech Inc

Inventors

• Shrivastava Prachi
• Chin Yuan Tung
• Boone Thomas
• Pinarbasi Mustafa

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H01L43/08

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H01L43/12 Primary

  Electricity · mapped topic