Process for hard mask development for mram pillar formation using photolithography

Patent metadata

Field	Value
Publication number	US-2019207080-A1
Application number	US-201715857351-A
Country	US
Kind code	A1
Filing date	Dec 28, 2017
Priority date	Dec 28, 2017
Publication date	Jul 4, 2019
Grant date	—

Abstract

A method for fabricating an array of pillars. The method includes fabricating an MTJ (magnetic tunnel junction) film deposition metal stack on a CMOS wafer. The method selects between subsequent electron beam patterning for the wafer and photolithography patterning for the wafer. For electron beam patterning, an electron beam lithography hard mask is deposited onto the metal stack, and an electron beam is used to pattern a first array of pillars into the electron beam lithography hard mask to produce a first resulting pillar array. For photolithography patterning, a photolithography hard mask is deposited onto the metal stack, and photolithography is used to pattern a second array of pillars into the photolithography hard mask to produce a second resulting pillar array. The first resulting pillar array is substantially the same as the second resulting pillar array.

First claim

1 . A method for fabricating an array of pillars, the method comprising:
fabricating an MTJ (magnetic tunnel junction) film deposition metal stack on a CMOS wafer;
depositing a photolithography hard mask onto the metal stack;
using photolithography to pattern an array of pillars into the photolithography hard mask to produce a resulting pillar array.

2 . The method of claim 1 , wherein the photolithography hard mask comprises a multilayer photolithography hard mask.

3 . The method of claim 2 , wherein the multilayer photolithography hard mask includes a bottom antireflective coating layer (BARC).

4 . The method of claim 1 , wherein reactive ion etching (REI) etches the photolithography hard mask to form hard mask pillars on top of the metal stack.

5 . The method of claim 1 , wherein the photolithography hard mask comprises a multilayer photolithography hard mask comprising a bottom antireflective coating (BARC) layer, a first hard mask layer, and a second hard mask layer.

6 . The method of claim 5 , wherein the first hard mask layer comprises tantalum nitride and the second hard mask layer comprises silicon oxide.

7 . The method of claim 1 , wherein the wafer produced using photolithography patterning proceeds through a subsequent MTJ fabrication process.

8 . A method for producing pillar arrays in a wafer fabrication process, the method comprising:
fabricating an MTJ (magnetic tunnel junction) film deposition metal stack on a CMOS wafer; selecting between subsequent electron beam patterning for the wafer and photolithography patterning for the wafer; for electron beam patterning, depositing an electron beam lithography hard mask onto the metal stack, and using an electron beam to pattern a first array of pillars into the electron beam lithography hard mask to produce a first resulting pillar array; for photolithography patterning, depositing a multilayer photolithography hard mask onto the metal stack, and using photolithography to pattern a second array of pillars into the multilayer photolithography hard mask to produce a second resulting pillar array, wherein the first resulting pillar array is substantially the same as the second resulting pillar array.

9 . The method of claim 8 , wherein the reactive ion etch process etches the electron beam lithography hard mask to form hard mask pillars on top of the metal stack.

10 . The method of claim 8 , wherein reactive ion etching (REI) etches the multilayer photolithography hard mask to form hard mask pillars on top of the metal stack.

11 . The method of claim 8 , wherein the multilayer photolithography hard mask comprises a bottom antireflective coating (BARC) layer, a first hard mask layer, and a second hard mask layer.

12 . The method of claim 11 , wherein the first hard mask layer comprises tantalum nitride and the second hard mask layer comprises silicon oxide.

13 . The method of claim 8 , wherein a first plurality of wafers produced using electron beam patterning and a second plurality of wafers produced using photolithography patterning proceed through a common subsequent MTJ fabrication process.

14 . A method for manufacturing an MRAM device, the method comprising:
fabricating an MTJ (magnetic tunnel junction) film deposition metal stack on a CMOS wafer; selecting between subsequent electron beam patterning for the wafer and photolithography patterning for the wafer; for electron beam patterning, depositing an electron beam lithography hard mask onto the metal stack, and using an electron beam to pattern a first array of pillars into the electron beam lithography hard mask to produce a first resulting pillar array; for photolithography patterning, depositing a multilayer photolithography hard mask onto the metal stack, and using photolithography to pattern a second array of pillars into the multilayer photolithography hard mask to produce a second resulting pillar array, wherein the first resulting pillar array is substantially the same as the second resulting pillar array; and outputting a first plurality of wafers produced with electron beam patterning and a second plurality of wafers produced with photolithography patterning through a common subsequent MTJ fabrication process.

15 . (canceled)

16 . The method of claim 14 , wherein the reactive ion etch process etches the electron beam lithography hard mask to form hard mask pillars on top of the metal stack.

17 . The method of claim 14 , wherein reactive ion etching (REI) etches the photolithography hard mask to form hard mask pillars on top of the metal stack.

18 . The method of claim 14 , wherein the photolithography hard mask comprises a multilayer photolithography hard mask comprising a bottom antireflective coating (BARC) layer, a first hard mask layer, and a second hard mask layer.

19 . The method of claim 14 , wherein the photolithography hard mask is over exposed with multiple dose conditions to achieve a desired critical dimension target on a completed wafer.

20 . The method of claim 19 , wherein multiple REI processes are utilized to trim the photolithography hard mask to achieve the desired critical dimension target.

Assignees

• Spin Transfer Tech Inc

Inventors

• Shrivastava Prachi
• Liu Daniel
• Chin Yuan Tung

Classifications

• H01L43/12

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H01L43/02 Primary

  Electricity · mapped topic

• H10N50/01

  Manufacture or treatment · CPC title

• H10B61/00 Primary

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title