Multiple gate length device with self-aligned top junction

Patent metadata

Field	Value
Publication number	US-2019206743-A1
Application number	US-201815860840-A
Country	US
Kind code	A1
Filing date	Jan 3, 2018
Priority date	Jan 3, 2018
Publication date	Jul 4, 2019
Grant date	—

Abstract

A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.

First claim

What is claimed is:

1 . A method of making a vertical FinFET device comprising:
forming a plurality of fins over a semiconductor substrate; forming a bottom source/drain region over the substrate and adjacent to the fins; forming a sacrificial gate having a first gate length over the substrate and surrounding the fins; forming a block mask over the sacrificial gate within a first device region of the substrate; modifying the sacrificial gate within a second device region of the substrate to form a second gate length different from the first gate length; treating portions of the fins disposed above the sacrificial gate after modifying the sacrificial gate within the second device region to form treated regions; etching the treated regions of the fins selectively with respect to untreated regions of the fins to remove the treated regions; and forming a top source/drain region over the untreated regions of the fins.

2 . The method of claim 1 , wherein the modifying comprises etching the sacrificial gate within the second device region to decrease the first gate length to the second gate length.

3 . The method of claim 2 , wherein the second gate length is 2% to 20% less than the first gate length.

4 . The method of claim 1 , wherein the modifying comprises forming a supplemental gate over the sacrificial gate in the second device region.

5 . The method of claim 4 , wherein the sacrificial gate thickness and the supplemental sacrificial gate thickness together define the second gate length and the second gate length is 2% to 20% greater than the first gate length.

6 . The method of claim 1 , wherein the treating comprises plasma doping or amorphizing.

7 . The method of claim 1 , further comprising forming a top spacer layer over sidewalls of the treated regions of the fins prior to selectively etching the treated regions of the fins.

8 . The method of claim 1 , wherein forming the top source/drain region comprises forming an epitaxial buffer layer having a first dopant content directly over each untreated region, and forming an epitaxial main layer having a second dopant content greater than the first dopant content directly over the epitaxial buffer layer.

9 . The method of claim 1 , further comprising:
removing the block mask from within the first device region; removing the sacrificial gate from within the first and second device regions; and forming a gate stack over sidewalls of the fins, wherein the gate stack comprises a gate dielectric layer formed directly over the fins and a gate conductor formed over the gate dielectric layer.

10 . A method of making a vertical FinFET device comprising:
forming a plurality of fins over a semiconductor substrate; forming a bottom source/drain region over the substrate and adjacent to the fins; forming a sacrificial gate having a first gate length over the substrate and surrounding the fins; forming a block mask over the sacrificial gate within a first device region of the substrate; modifying the sacrificial gate within a second device region of the substrate to form a second gate length different from the first gate length; removing the block mask from within the first device region; treating portions of the fins disposed above the sacrificial gate within the first device region and the second device region after modifying the sacrificial gate within the second device region to form treated regions; etching the treated regions of the fins selectively with respect to untreated regions of the fins to remove the treated regions; forming a top source/drain region over the untreated regions of the fins; removing the sacrificial gate from within the first and second device regions; and forming a gate stack over sidewalls of the fins, wherein the gate stack comprises a gate dielectric layer formed directly over the fins and a gate conductor formed over the gate dielectric layer.

11 . The method of claim 10 , wherein the gate length of the sacrificial gate within the second device region is 2% to 20% less than the gate length of the sacrificial gate within the first device region.

12 . The method of claim 10 , wherein treating the portions of the fins disposed above the sacrificial gate comprises doping to form a doped region within each fin.

13 . The method of claim 12 , wherein the doping is performed after modifying the sacrificial gate within the second device region.

14 . The method of claim 12 , wherein the fins are doped with arsenic.

15 . The method of claim 12 , wherein the top source/drain region is formed directly over an undoped region of each of the fins.

16 . A method of making a vertical FinFET device comprising:
forming a plurality of fins over a semiconductor substrate in a first and a second device region; forming a bottom source/drain region over the substrate and adjacent to the fins; forming a sacrificial gate having a first gate length over the substrate and surrounding the fins; modifying the sacrificial gate within the second device region of the substrate to have a second gate length different from the first gate length within the first device region; removing portions of the fins disposed above the sacrificial gate; forming a top source/drain region over the remaining portions of the fins; removing the sacrificial gate from within the first and second device regions; and forming a gate stack over sidewalls of the fins, wherein the gate stack comprises a gate dielectric layer formed directly over the fins and a gate conductor formed over the gate dielectric layer.

17 . The method of claim 16 , wherein modifying the sacrificial gate comprises etching the sacrificial gate within the second device region to have the second gate length less than the first gate length.

18 . The method of claim 16 , wherein modifying the sacrificial gate comprises forming a supplemental gate over the sacrificial gate in the second device region.

19 . The method of claim 16 , wherein removing portions of the fins comprises:
treating portions of the fins disposed above the sacrificial gate within the first device region and the second device region after modifying the sacrificial gate within the second device region to form treated regions; and etching the treated regions of the fins selectively with respect to untreated regions of the fins to remove the treated regions.

Assignees

• Globalfoundries Inc

Inventors

• Zang Hui
• Peng Jianwei
• Qi Yi
• Lo Hsien-Ching
• Ciavatti Jerome
• Xie Ruilong

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H01L27/088

  Electricity · mapped topic

• H01L21/823487 Primary

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic