Forward error control coding

Patent metadata

Field	Value
Publication number	US-2019199378-A1
Application number	US-201916292693-A
Country	US
Kind code	A1
Filing date	Mar 5, 2019
Priority date	Dec 23, 2014
Publication date	Jun 27, 2019
Grant date	—

Abstract

Disclosed embodiments include a device having a transmitter circuit that includes an input to receive data blocks that are part of a set of incoming data, a parity bit generator to append a number of parity bits to each of the received data blocks, a first encoder to apply a first type of encoding to create first coded blocks based on the received data blocks and the parity bits, an interleaver to interleave symbols in the first coded blocks to create additional blocks having a block size, wherein the number of parity bits appended to each of the received blocks is based on the block size, and a second encoder to apply a second type of encoding to create an output based on the additional blocks, wherein the second type of encoding is different from the first type of encoding.

First claim

What is claimed is:

1 . An electronic device comprising:
a transmitter circuit having:
an input to receive data blocks, the data blocks being at least part of a set of incoming data;
a parity bit generator to append a number of parity bits to each of the received data blocks;
a first encoder to apply a first type of encoding to create first coded blocks based on the received data blocks and the parity bits;
an interleaver to interleave symbols in the first coded blocks to create additional blocks having a block size, wherein the number of parity bits appended to each of the received blocks is based on the block size; and
a second encoder to apply a second type of encoding to create an output based on the additional blocks, wherein the second type of encoding is different from the first type of encoding.

2 . The electronic device of claim 1 , wherein the first type of encoding is Reed-Solomon (RS) encoding and the first coded blocks are RS blocks.

3 . The electronic device of claim 1 , wherein the second type of encoding is turbo encoding.

4 . The electronic device of claim 1 , wherein:
the first type of encoding is Reed-Solomon (RS) encoding; and the second type of encoding is turbo encoding.

5 . The electronic device of claim 1 , wherein first coded blocks have a size that matches an input block size of the second encoder so that an integer number of the first coded blocks are interleaved by the interleaver to create the additional blocks.

6 . The electronic device of claim 1 , wherein the parity bits are cyclic redundancy check (CRC) bits.

7 . The electronic device of claim 1 , wherein the interleaver is configured to sequentially fill the additional blocks with symbols from successive first coded blocks.

8 . The electronic device of claim 1 , wherein the electronic device is a base station and the transmitter is a transmitter of the base station.

9 . The electronic device of claim 1 , wherein the base station is a Long Term Evolution (LTE) base station.

10 . The electronic device of claim 1 , wherein the transmitter circuit is operable to transmit the output created by the second encoder.

11 . An electronic device comprising:
a receiver circuit having:
an input to receive a signal;
a first decoder to apply a first type of decoding to the signal to create first decoded output blocks;
a de-interleaver to de-interleave the first decoded output blocks to produce additional blocks;
a second decoder to apply a second type of decoding to the additional blocks to produce second decoded output blocks, wherein each second decoded output block includes a number of parity bits, and wherein the second type of decoding is different from the first type of decoding; and
a parity bit generator checking circuit to evaluate the parity bits in each of the decoded output data blocks, wherein the number of parity bits is based on a block size of the first decoded output blocks.

12 . The electronic device of claim 11 , wherein the first type of decoding is turbo decoding.

13 . The electronic device of claim 11 , wherein the second type of decoding is Reed-Solomon (RS) decoding.

14 . The electronic device of claim 11 , wherein:
the first type of decoding is turbo decoding; the second type of decoding is Reed-Solomon (RS) decoding; the additional blocks produced by the de-interleaver are RS input blocks.

15 . The electronic device of claim 11 , wherein the additional blocks have a size that matches an output block size of the first decoder so that an integer number of the additional blocks are de-interleaved from the first decoded output blocks.

16 . The electronic device of claim 11 , wherein the parity bits are cyclic redundancy check (CRC) bits.

17 . The electronic device of claim 11 , wherein the electronic device is a base station and the receiver is a receiver of the base station.

18 . The electronic device of claim 11 , wherein the base station is a Long Term Evolution (LTE) base station.

Assignees

• Texas Instruments Inc

Inventors

• Mansour Mohamed Farouk
• Roh June Chul
• Hosur Srinath

Classifications

• H03M13/2957 Primary

  Turbo codes and decoding · CPC title

• H03M13/09

  Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit · CPC title

• H03M13/2966

  Turbo codes concatenated with another code, e.g. an outer block code · CPC title

• H03M13/27 Primary

  using interleaving techniques · CPC title

• H03M13/618

  Shortening and extension of codes · CPC title