Methods and apparatus to generate a circuit protection voltage

Patent metadata

Field	Value
Publication number	US-2019199339-A1
Application number	US-201715853215-A
Country	US
Kind code	A1
Filing date	Dec 22, 2017
Priority date	Dec 22, 2017
Publication date	Jun 27, 2019
Grant date	—

Abstract

Apparatus, methods and systems to produce a protection voltage are disclosed. The apparatus includes circuitry to deliver a first supply voltage to a plurality of circuits, where the first supply voltage has a first magnitude, circuitry to deliver a second supply voltage to a part of the plurality of circuits, where the second supply voltage has a second magnitude, and circuitry to deliver a protection voltage to the part of the plurality of circuits when the second supply voltage is LOW and the first supply voltage is HIGH. The protection voltage has a magnitude that is a fraction of the magnitude of the first supply voltage. The apparatus includes circuitry that causes the delivery of the second supply voltage to the part of the plurality of circuits when the second supply voltage is turned HIGH subsequent to the second supply voltage being LOW when the first supply voltage is HIGH.

First claim

What is claimed is:

1 . An apparatus to produce a protection voltage, the apparatus comprising:
circuitry to deliver a first supply voltage to a plurality of circuits, the first supply voltage having a first magnitude; circuitry to deliver a second supply voltage to a subset of the plurality of circuits, the second supply voltage having a second magnitude; circuitry to deliver a protection voltage to the subset of the plurality of circuits when the second supply voltage is LOW and the first supply voltage is HIGH, the protection voltage having a magnitude that is a fraction of the magnitude of the first supply voltage; and circuitry to cause a delivery of the second supply voltage to the subset of the plurality of circuits when the second supply voltage is turned HIGH subsequent to the second supply voltage being LOW when the first supply voltage is HIGH.

2 . The apparatus of claim 1 , wherein the circuitry to deliver the protection voltage includes a voltage divider and a gating transistor that prevents a voltage having the first magnitude from being applied to the subset of the plurality of circuits during a power-up/power-down operation.

3 . The apparatus of claim 1 , wherein the protection voltage is supplied through a transistor that is gated by the second supply voltage.

4 . The apparatus of claim 1 , wherein the first supply voltage is an input/output (I/O) circuit supply voltage.

5 . The apparatus of claim 1 , wherein the second supply voltage is a core logic supply voltage.

6 . The apparatus of claim 1 , wherein the protection voltage is produced from the first supply voltage through a plurality of resistors.

7 . The apparatus of claim 1 , wherein the first supply voltage has a greater magnitude than the second supply voltage.

8 . The apparatus of claim 1 , wherein the circuity to deliver the first supply voltage includes a transistor that is gated by a first inverter and a second inverter coupled in series, the first inverter to provide logic inversion from the second supply voltage and converted into a first supply voltage domain, and the second inverter having a same polarity as the second supply voltage in the first supply voltage domain.

9 . The apparatus of claim 1 , wherein the subset of the plurality of circuits including a receiver amplifier, the receiver amplifier including:
a first pair of transistors including a first transistor and a second transistor, the first and second transistors gated by the protection voltage when the second supply voltage is LOW and the first supply voltage is HIGH; a second pair of transistors including a third transistor and a fourth transistor to convert differential current gain to voltage gate at an output, a drain of the third transistor connected to a drain of the first transistor, a drain of the fourth transistor connected to a drain of the second transistor; and a third pair of transistors including a fifth transistor and a sixth transistor to provide voltage to current gain, the fifth and sixth transistors gated by positive and negative input terminals, respectively, a drain of the fifth transistor is connected to a source of the first transistor, and a drain of the sixth transistor is connected to a source of the second transistor.

10 . The apparatus of claim 9 , wherein the receiver amplifier further including:
a fourth pair of transistors including a seventh transistor and an eighth transistor to form a current mirror to convert input current through a bias voltage to a drain of the seventh transistor, the drain of the seventh transistor connected to sources of the fifth and sixth transistors.

11 . An input/output (I/O) circuit, the I/O circuit comprising:
receiver circuitry; data driver circuitry; and protective voltage producing circuitry, the protective voltage producing circuitry comprising:
circuitry to distribute a first supply voltage to a plurality of circuits, the first supply voltage having a first voltage level;
circuitry to distribute a second supply voltage to a part of the plurality of circuits, the second supply voltage having a second voltage level;
circuitry to distribute a protection voltage to the part of the plurality of circuits when the second supply voltage is LOW and the first supply voltage is HIGH, the protection voltage having a voltage level that is a fraction of the voltage level of the first supply voltage; and
circuitry to trigger a distribution of the second supply voltage to the part of the plurality of circuits when the second supply voltage is turned HIGH subsequent to the second supply voltage being LOW when the first supply voltage is HIGH.

12 . The I/O circuit of claim 11 , wherein the circuitry to distribute a protection voltage includes a voltage divider and a gating transistor that prevents a voltage having the first magnitude from being applied to the part of the plurality of circuits during a power-up/power-down operation.

13 . The I/O circuit of claim 11 , wherein the protection voltage is supplied through a transistor that is gated by the second supply voltage.

14 . The I/O circuit of claim 11 , wherein the first supply voltage is an input/output (I/O) circuit supply voltage.

15 . The I/O circuit of claim 11 , wherein the second supply voltage is a core logic supply voltage.

16 . The I/O circuit of claim 11 , wherein the part of the plurality of circuits includes a data driver, the data driver including a first pair of transistors including a first transistor and a second transistor, the first transistor gated by the protection voltage when the second supply voltage is LOW and the first supply voltage is HIGH.

17 . The I/O circuit of claim 16 , wherein the data driver further includes a second pair of transistors, the second transistor being gated by the second pair of transistors.

18 . A method to produce a protection voltage, the method comprising:
supplying a first supply voltage to a plurality of circuits, the first supply voltage having a first magnitude; supplying a second supply voltage to a part of the plurality of circuits, the second supply voltage having a second magnitude; supplying a protection voltage to the part of the plurality of circuits when the second supply voltage is LOW and the first supply voltage is HIGH, the protection voltage having a magnitude that is a fraction of the magnitude of the first supply voltage; and delivering the second supply voltage to the part of the plurality of circuits when the second supply voltage is turned HIGH subsequent to the second supply voltage being LOW when the first supply voltage is HIGH.

19 . The method of claim 18 , wherein the first supply voltage is prevented from being used as the protection voltage during power-up/power down by a voltage divider and a gating transistor.

20 . The method of claim 18 , wherein the protection voltage is supplied through a transistor that is gated by the second supply voltage.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Zhou Dacheng

Classifications

• H03K17/005

  with several inputs only · CPC title

• H03K17/002

  Switching arrangements with several input- or output terminals (code converters H03M5/00, H03M7/00) · CPC title

• H03K17/51

  characterised by the components used (H03K17/04 - H03K17/30, H03K17/94 take precedence) · CPC title

• H03K17/56

  by the use, as active elements, of semiconductor devices (using diodes H03K17/74) · CPC title

• H03K17/042

  by feedback from the output circuit to the control circuit {(H03K17/0403, H03K17/0406 take precedence)} · CPC title