Semiconductor apparatus comprising a plurality of current sink units

Patent metadata

Field	Value
Publication number	US-2019198102-A1
Application number	US-201916291879-A
Country	US
Kind code	A1
Filing date	Mar 4, 2019
Priority date	Aug 22, 2013
Publication date	Jun 27, 2019
Grant date	—

Abstract

A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.

First claim

What is claimed is:

1 . A semiconductor apparatus, comprising:
a plurality of memory elements; a read/write circuit electrically connected to the plurality of memory elements, the read/write circuit configured to amplify a current or a voltage outputted from the plurality of memory elements and to apply a current or a voltage to the plurality of memory elements; a driving unit configured to provide different voltages to the plurality of memory elements; and a plurality of current sink units connected to the plurality of memory elements, respectively, each of the current sink unit configured to sink a current flowing in each of the memory cells to a ground terminal, wherein current sink amounts of each of the current sink units are different.

2 . The semiconductor apparatus according to the claim 1 , wherein the driving unit is configured to apply a gradually decreasing voltage to the memory elements as a distance between the read/write circuit and the memory element is decreased.

3 . The semiconductor apparatus according to the claim 1 , wherein the current sink amount is gradually increased as a distance between the read/write circuit and the memory element is decreased.

4 . The semiconductor apparatus according to the claim 1 , further comprising:
a decoding circuit configured to generate a column select signal and a plurality of word line select signals.

5 . The semiconductor apparatus according to the claim 4 , wherein the driving unit is configured to provide the different voltages to the plurality of memory elements in response to the column select signal.

6 . The semiconductor memory apparatus according to claim 5 ,
wherein the driving unit comprises: a driving transistor configured to provide a driving voltage in response to the column select signal; and a plurality of resistor elements electrically coupled in series to be inputted with an output of the driving transistor, wherein the memory elements are electrically coupled to respective nodes where the plurality of resistor elements are electrically coupled.

7 . The semiconductor memory apparatus according to claim 5 , further comprising:
a sink current control unit configured to generate the plurality of sink voltages with different voltage levels in response to a word line select signal which is enabled among the plurality of word line select signals, wherein the plurality of current sink units is configured to be driven in response to the plurality of sink voltages.

8 . The semiconductor memory apparatus according to claim 7 , wherein the sink current control unit is configured to provide a sink voltage with a higher voltage level to the current sink unit electrically coupled with the memory element close to the read/write circuit than the current sink unit electrically coupled with the memory element far from the read/write circuit.

9 . The semiconductor memory apparatus according to claim 8 , wherein the sink current control unit comprises:
a voltage dividing section configured to supply a first word line driving voltage and a second word line driving voltage to both ends, respectively, of a plurality of resistor elements electrically coupled in series, in response to a voltage supply signal, and generate the plurality of sink voltages; and a plurality of switching sections configured to output one of the plurality of sink voltages in response to a word line select signal which is enabled among the plurality of word line select signals.

Assignees

• Sk Hynix Inc

Inventors

• Yoon Jung Hyuk
• Shin Yoon Jae

Classifications

• G06F3/0673

  Single storage device · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C13/0023

  Address circuits or decoders · CPC title