Methods and structures for cutting lines or spaces in a tight pitch structure

Patent metadata

Field	Value
Publication number	US-2019189446-A1
Application number	US-201715846711-A
Country	US
Kind code	A1
Filing date	Dec 19, 2017
Priority date	Dec 19, 2017
Publication date	Jun 20, 2019
Grant date	—

Abstract

A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, forming a plurality of spacers on the hardmask layer, wherein the plurality of spacers comprise a first set of spacers and a second set of spacers, reducing a height of each spacer of the second set of spacers to be less than a height of each spacer of the first set of spacers, removing one or more spacers from at least one of the first set of spacers and the second set of spacers, transferring a pattern of remaining spacers to the hardmask layer to form a plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions to the substrate to form one of a plurality of patterned substrate portions and a plurality of openings in the substrate.

First claim

1 . A method for manufacturing a semiconductor device, comprising:
forming a hardmask layer on a substrate; forming a plurality of spacers on the hardmask layer, wherein the plurality of spacers comprise a first set of spacers and a second set of spacers; reducing a height of each spacer of the second set of spacers to be less than a height of each spacer of the first set of spacers; removing one or more spacers from at least one of the first set of spacers and the second set of spacers; transferring a pattern of remaining spacers to the hardmask layer to form a plurality of patterned hardmask portions; transferring a pattern of the plurality of patterned hardmask portions to the substrate to form one of a plurality of patterned substrate portions and a plurality of openings in the substrate; forming a plurality of mandrels on the hardmask layer, wherein the plurality of spacers are formed on sides of the plurality of mandrels; and depositing a mandrel material on the hardmask layer to fill in vacant areas formed by the reducing of the height of each spacer of the second set of spacers.

2 . (canceled)

3 . (canceled)

4 . The method according to claim 1 , further comprising planarizing the mandrel material so that a top surface of the mandrel material is coplanar with a top surface of each spacer of the first set of spacers.

5 . The method according to claim 4 , wherein the removing of the one or more spacers from at least one of the first set of spacers and the second set of spacers comprises selectively removing each spacer of the first set of spacers with respect to the mandrel material.

6 . The method according to claim 5 , further comprising forming a plurality of dielectric material portions on the hardmask layer in place of the removed first set of spacers, wherein the plurality of dielectric material portions can be selectively etched with respect to a material of the plurality of spacers.

7 . The method according to claim 6 , further comprising selectively removing one or more of the plurality of dielectric material portions with respect to the second set of spacers.

8 . The method according to claim 7 , further comprising transferring a pattern of remaining dielectric material portions to the hardmask layer to form an additional plurality of patterned hardmask portions.

9 . The method according to claim 6 , wherein the removing of the one or more spacers from at least one of the first set of spacers and the second set of spacers comprises selectively removing a spacer of the second set of spacers with respect to the plurality of dielectric material portions.

10 . A method for manufacturing a semiconductor device, comprising:
forming a hardmask layer on a substrate; forming a plurality of spacers on the hardmask layer, wherein the plurality of spacers comprise a first set of spacers and a second set of spacers; reducing a height of each spacer of the second set of spacers to be less than a height of each spacer of the first set of spacers; removing one or more spacers from at least one of the first set of spacers and the second set of spacers; transferring a pattern of remaining spacers to the hardmask layer to form a plurality of patterned hardmask portions; and transferring a pattern of the plurality of patterned hardmask portions to the substrate to form one of a plurality of patterned substrate portions and a plurality of openings in the substrate; wherein the removing of the one or more spacers from at least one of the first set of spacers and the second set of spacers comprises removing each spacer of the first set of spacers.

11 . The method according to claim 10 , further comprising forming a plurality of dielectric material portions on the hardmask layer in place of the removed first set of spacers, wherein the plurality of dielectric material portions can be selectively etched with respect to a material of the plurality of spacers.

12 . The method according to claim 4 , further comprising forming a mask on the planarized mandrel material, wherein the mask leaves exposed a spacer of the first set of spacers.

13 . The method according to claim 12 , wherein the removing of the one or more spacers from at least one of the first set of spacers and the second set of spacers comprises removing the exposed spacer of the first set of spacers with respect to the mandrel material.

14 . The method according to claim 4 , further comprising removing a portion of each spacer of the first set of spacers to reduce a height of each spacer of the first set of spacers to be less than a height of each spacer of the second set of spacers.

15 . The method according to claim 14 , further comprising further planarizing the mandrel material so that a top surface of the mandrel material is coplanar with a top surface of each spacer of the second set of spacers.

16 . The method according to claim 14 , further comprising forming a mask on the further planarized mandrel material, wherein the mask leaves exposed a spacer of the second set of spacers.

17 . The method according to claim 16 , wherein the removing of the one or more spacers from at least one of the first set of spacers and the second set of spacers comprises removing the exposed spacer of the second set of spacers with respect to the mandrel material.

18 . The method according to claim 1 , wherein the substrate comprises one of a semiconductor material and a dielectric material.

19 . A method for manufacturing a semiconductor device, comprising:
forming a hardmask layer on a substrate; forming a plurality of mandrel portions on the hardmask layer; forming a plurality of spacers on sides of the plurality of mandrel portions; reducing a height of each spacer on a first side of each mandrel portion of the plurality of mandrel portions so that spacers on opposite sides of each mandrel portion have different heights from each other; removing one or more spacers of the plurality of spacers; transferring a pattern of remaining spacers to the hardmask layer to form a plurality of patterned hardmask portions; and transferring a pattern of the plurality of patterned hardmask portions to the substrate to form one of a plurality of patterned substrate portions and a plurality of openings in the substrate.

20 . A method for manufacturing a semiconductor device, comprising:
forming a plurality of amorphous silicon (a-Si) portions on a hardmask layer; forming a plurality of dielectric spacers on sides of the plurality of a-Si portions; reducing a height of each spacer on a first side of each a-Si portion of the plurality of a-Si portions so that spacers on opposite sides of each a-Si portion have different heights from each other; removing one or more spacers of the plurality of spacers; using a pattern of remaining spacers on the hardmask layer as masks, removing exposed portions of the hardmask layer to form a plurality of patterned hardmask portions; and forming one of a plurality of patterned substrate portions and a plurality of openings in the substrate corresponding to the plurality of patterned hardmask portions.

Assignees

• IBM

Inventors

• Xu Peng
• Cheng Kangguo
• Lee Choonghyun
• Li Juntao

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P76/4083

  characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks · CPC title

• H10P76/4088 Primary

  Processes for improving the resolution of the masks · CPC title

• H01L21/0338 Primary

  Electricity · mapped topic

• H01L21/0337

  Electricity · mapped topic