Common platform for one-level memory architecture and two-level memory architecture

Patent metadata

Field	Value
Publication number	US-2019179531-A1
Application number	US-201916274866-A
Country	US
Kind code	A1
Filing date	Feb 13, 2019
Priority date	Dec 24, 2013
Publication date	Jun 13, 2019
Grant date	—

Abstract

A processor includes a first memory interface to be coupled to a plurality of memory module sockets located off-package, a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package, and a multi-level memory controller (MLMC). The MLMC is to: control the memory modules disposed in the plurality of memory module sockets as main memory in a one-level memory (1LM) configuration; detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of a low-power memory module disposed in one of the memory module sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and control the low-power memory module as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.

First claim

What is claimed is:

1 . A processor comprising:
a first memory interface to be coupled to a plurality of memory module sockets located off-package of the processor; a second memory interface to be coupled to a non-volatile memory (NVM) socket located off-package of the processor; and a multi-level memory controller (MLMC) coupled to the first memory interface and to the second memory interface, the MLMC to:
control one or more memory modules disposed in the plurality of memory module sockets as main memory in a one-level memory (1LM) configuration;
detect a switch from a 1LM mode of operation to a two-level memory (2LM) mode of operation in response to a basic input/output system (BIOS) detection of at least one low-power memory module disposed in one of the plurality of memory module sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and
control the at least one low-power memory module as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.

2 . The processor of claim 1 , wherein the MLMC comprises a multiplexer to select between control of the one or more memory modules, the at least one low-power memory module, and the NVM device according to the 1LM configuration or the 2LM configuration in response to receipt of an indicator that specifies memory configuration, and wherein the MLMC further comprises:
a 2LM cache controller; a near memory (NM) controller coupled to the first memory interface; a far memory (FM) controller coupled to the second memory interface and the 2LM cache controller; and a system agent arbiter coupled to a requesting unit and the 2LM cache controller; and wherein the multiplexer comprises a first input coupled to an output of the 2LM cache controller, a second input coupled to an output of the system agent arbiter, and an output coupled to the NM controller, wherein the multiplexer is to select between the first input and the second input according to the indicator.

3 . The processor of claim 1 , wherein the first memory interface is a double data rate (DDR) memory interface, which further comprises a DDR voltage regulator to provide a 1LM voltage to the one or more memory modules in the 1LM configuration and to additionally provide a 2LM voltage to the at least one low-power memory module in the 2LM configuration.

4 . The processor of claim 1 , wherein the one or more memory modules are dynamic random access memory (DRAM)-based memory modules.

5 . The processor of claim 4 , wherein the DRAM on the DRAM-based memory modules comprises double data rate (DDR) DRAM, and wherein the DDR DRAM is at least one of DDR3 DRAM, DDR3L, or DDR4 DRAM.

6 . The processor of claim 1 , wherein the at least one low-power memory module is one of low power DDR3 (LPDDR3) or low power DDR4 (LPDDR4) DRAM in the 2LM configuration.

7 . The processor of claim 1 , wherein the second memory interface is one of an expansion card interface or an M.2 standard interface.

8 . The processor of claim 1 , wherein, in the 2LM configuration, the MLMC is to interact with the at least one low-power memory module as near memory and with the NVM device as far memory.

9 . A system on chip (SoC) comprising:
a plurality of functional units; and a multi-level memory controller (MLMC) to provide a common platform for a one-level memory (1LM) configuration and a two-level memory (2LM) configuration, wherein the MLMC comprises:
a 2LM cache controller;
a near memory (NM) controller coupled to a first memory interface to communicate with a plurality of memory module sockets located off-package of the SoC;
a far memory (FM) controller coupled to a second memory interface and the 2LM cache controller, the second memory interface to communicate with a non-volatile memory (NVM) socket located off-package of the SoC; and
a system agent arbiter coupled to the plurality of functional units and the 2LM cache controller; and
wherein the MLMC is to:
control one or more memory modules disposed in the plurality of memory module sockets as main memory in the 1LM configuration;
detect a switch from a 1LM mode of operation to a 2LM mode of operation in response to a basic input/output system (BIOS) detection of at least one low-power memory module disposed in one of the plurality of memory module sockets and a NVM device disposed in the NVM socket in a 2LM configuration; and
control the at least one low-power memory module as cache in the 2LM configuration in response to detection of the switch from the 1LM mode of operation to the 2LM mode of operation.

10 . The SoC of claim 9 , wherein the system agent arbiter is to:
receive a memory request from a functional unit of the plurality of functional units; and responsive to detection of operation in the 2LM mode of operation, direct the memory request to the 2LM cache controller.

11 . The SoC of claim 10 , wherein the 2LM cache controller is further to:
perform a lookup to map the memory request to one of the NM controller or the FM controller; responsive to a map of the memory request to the NM controller, direct the memory request to the NM controller; and responsive to a map of the memory request to the FM controller, direct the memory request to the FM controller.

12 . The SoC of claim 9 , wherein the first memory interface is a double data rate (DDR) memory interface and the second memory interface is a NVM drive interface.

13 . The SoC of claim 12 , wherein the DDR memory interface is to interact with at least one of DDR3 dynamic random access memory (DRAM), DDR3L, or DDR4 DRAM in the 1LM configuration and at least one of low-power DDR3 (LPDDR3) or low-power DDR4 (LPDDR4) DRAM in the 2LM configuration.

14 . The SoC of claim 9 , wherein the MLMC further comprises a multiplexer comprising a first input coupled to an output of the 2LM cache controller, a second input coupled to an output of the system agent arbiter, and an output coupled to the NM controller, wherein the multiplexer is to select between the first input and the second input based on an indicator that specifies the 1LM configuration or the 2LM configuration.

15 . A method comprising:
detecting, by a processor, whether a second memory device is available in a computer platform comprising the processor and a first memory device, the first memory device including a plurality of memory modules, wherein the second memory device is a non-volatile memory (NVM) device; detecting a switch, by a basic input/output system (BIOS) of the computer platform, from a one-level memory (1LM) mode of operation to a two-level memory (2LM) mode of operation in response to detecting availability of the second memory device and at least one low-power memory module as one of the plurality of memory modules of the first memory device; and controlling, by a multi-level memory controller (MLMC) of the processor, the at least one low-power memory module as cache in a 2LM configuration of the MLMC in response to detecting the switch from the 1LM mode of operation to the 2LM mode of operation.

16 . The method of claim 15 , wherein when the second memory device is not available:
presenting to software, by the MLMC, a first addressable memory space of system memory based on a first capacity of the first memory device present in the computer platform in a 1LM configuration; and controlling, by the MLMC, the plurality of memory modules as main memory in the 1LM configuration.

17 . The method of claim 16 , wherein responsive to detecting the switch from the 1LM mod

Assignees

• Intel Corp

Inventors

• Ray Joydeep
• George Varghese
• Sodhi Inder M
• Wilcox Jeffrey R

Classifications

• G06F15/781

  On-chip cache; Off-chip memory · CPC title

• G06F12/0638

  Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70) · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F2212/7206

  Reconfiguration of flash memory system · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title