Memory latency management

Patent metadata

Field	Value
Publication number	US-2019129792-A1
Application number	US-201815756039-A
Country	US
Kind code	A1
Filing date	Feb 27, 2018
Priority date	Mar 13, 2013
Publication date	May 2, 2019
Grant date	—

Abstract

Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed.

First claim

1 . An electronic device, comprising:
a central processing unit (CPU) package, further comprising:
a processor;
a local memory;
a memory interface; and
an integrated memory controller, further comprising logic to:
receive a request for data from the processor;
send the request for the data from the integrated memory controller to a remote controller of a remote nonvolatile memory device;
receive, at the integrated memory controller, the data from the remote controller of the remote nonvolatile memory device;
store the data in the local memory on the CPU package; and
receive an error correction code indicator associated with the data.

2 . The electronic device of claim 1 , wherein the local memory is synchronous dynamic random-access memory (SDRAM).

3 . The electronic device of claim 1 , wherein the remote nonvolatile memory device comprises three dimensional (3D) cross point memory.

4 . The electronic device of claim 1 , further comprising logic to:
determine that the error correction code indicator indicates that the data retrieved from the remote controller was error free; and in response to the determination that the data was error free, send the data from the local memory to the processor.

5 . The electronic device of claim 1 , further comprising logic to:
determine that the error correction code indicator indicates that the data retrieved from the remote controller includes at least one error; and in response to the determination that the data includes at least one error:
delete the data from the local memory; and
wait to receive corrected data from the remote controller of the remote nonvolatile memory device.

6 . The electronic device of claim 1 , wherein the local memory is synchronous dynamic random-access memory (SDRAM) and the remote nonvolatile memory device comprises three dimensional (3D) cross point memory.

7 . An electronic system, comprising:
a remote nonvolatile memory device including;
a memory bank; and
a remote controller;
a communication bus coupled to the remote nonvolatile memory device; and a central processing unit (CPU) package further comprising:
a processor;
a local memory;
a memory interface coupled to the communication bus; and
an integrated memory controller further comprising logic to:
receive a request for data from the processor;
send the request for the data from the integrated memory controller to the remote controller of the remote nonvolatile memory device over the communication bus;
receive, at the integrated memory controller, the data from the remote controller of the remote nonvolatile memory device;
store the data in the local memory on the CPU package; and
receive an error correction code indicator associated with the data.

8 . The electronic system of claim 7 , wherein the local memory is synchronous dynamic random-access memory (SDRAM).

9 . The electronic system of claim 7 , wherein the memory bank comprises three dimensional (3D) cross point memory.

10 . The electronic system of claim 7 , wherein the local memory is synchronous dynamic random-access memory (SDRAM) and the memory bank comprises three dimensional (3D) cross point memory.

11 . The electronic system of claim 7 , further comprising logic to:
determine that the error correction code indicator indicates that the data retrieved from the remote controller was error free; and in response to the determination that the data was error free, send the data from the local memory to the processor.

12 . The electronic system of claim 7 , further comprising logic to:
determine that the error correction code indicator indicates that the data retrieved from the remote controller includes at least one error; and in response to the determination that the data includes at least one error:
delete the data from the local memory; and
wait to receive corrected data from the remote controller of the remote nonvolatile memory device.

13 . The electronic system of claim 7 , wherein the remote controller further comprises remote controller logic to:
receive the request for the data from the integrated memory controller; retrieve the data from the memory bank; determine whether the communication bus is in an idle state; and in response to a determination that the communication bus is in an idle state, the remote controller logic is further configured to:
begin sending the data from the remote controller to the integrated memory controller over the communication bus while the data is being retrieved from the memory bank to the remote controller;
initiate an error correction code algorithm on the data while the data is being sent to the integrated memory controller; and
send an error correction code indicator to the integrated memory controller over the communication bus; or
in response to a determination that the communication bus is not in an idle state, the remote controller logic is further configured to:
initiate an error correction code algorithm on the data;
correct any errors in the data; and
subsequently send the data to the integrated memory controller over the communication bus.

14 . The electronic system of claim 13 , wherein, in response to the determination that the communication bus is in an idle state, the remote controller logic is further configured to:
estimate a delay time needed to execute the error correction code algorithm; and delay the beginning of sending the data from the remote controller to the integrated memory controller by the delay time.

15 . The electronic system of claim 14 , wherein, in response to the error correction code indicator indicating that the data contains at least one error, the remote controller logic is further configured to:
send, to the integrated memory controller, a retry error correction code indicator; correct the at least one error; and
send the corrected data over the communication bus to the integrated memory controller.

Assignees

• Intel Corp

Inventors

• Royer Jr Robert J
• Fanning Blaise
• Ooi Eng Hun

Classifications

• G06F12/0866

  for peripheral storage systems, e.g. disk cache · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title