Digital Silicon Microphone with Interpolation

Patent metadata

Field	Value
Publication number	US-2019123762-A1
Application number	US-201715790848-A
Country	US
Kind code	A1
Filing date	Oct 23, 2017
Priority date	Oct 23, 2017
Publication date	Apr 25, 2019
Grant date	—

Abstract

In accordance with an embodiment, a digital microphone interface circuit includes a delta-sigma analog-to-digital converter (ADC) having an input configured to be coupled to a microphone, a digital lowpass filter coupled to an output of the delta-sigma ADC, and a digital sigma-delta modulator coupled to an output of the digital lowpass filter. The delta-sigma ADC, the digital lowpass filter, and the digital sigma-delta modulator are configured to operate at different sampling frequencies.

First claim

1 . A microphone interface circuit comprising:
a delta-sigma analog-to-digital converter (ADC) configured to operate at a first sampling frequency, the delta-sigma ADC having an input configured to be coupled to a microphone; a digital lowpass filter coupled to an output of the delta-sigma ADC, the digital lowpass filter being configured to operate at a second sampling frequency; and a digital sigma-delta modulator coupled to an output of the digital lowpass filter, the digital sigma-delta modulator being configured to operate at a third sampling frequency, wherein at least one of the first sampling frequency and the third sampling frequency is higher than the second sampling frequency.

2 . The microphone interface circuit of claim 1 , further comprising a first digital interpolation filter coupled between the digital lowpass filter and the digital sigma-delta modulator, wherein the first sampling frequency is equal to the second sampling frequency, and the third sampling frequency is higher than the second sampling frequency.

3 . The microphone interface circuit of claim 1 , further comprising a digital decimation filter coupled between the delta-sigma ADC and the digital lowpass filter, wherein the first sampling frequency is higher than the second sampling frequency.

4 . The microphone interface circuit of claim 3 , further comprising a second digital interpolation filter coupled to the digital sigma-delta modulator, wherein the second sampling frequency is equal to the third sampling frequency.

5 . The microphone interface circuit of claim 4 , wherein the second digital interpolation filter is configured to upsample an output of the digital sigma-delta modulator by repeating each sample of the output of the digital sigma-delta modulator a number of times.

6 . The microphone interface circuit of claim 3 , further comprising a third digital interpolation filter coupled between the digital lowpass filter and the sigma-delta digital modulator, wherein the third sampling frequency is higher than the second sampling frequency.

7 . The microphone interface circuit of claim 1 , further comprising a Micro-Electro-Mechanical Systems (MEMS) microphone transducer coupled to the delta-sigma ADC.

8 . The microphone interface circuit of claim 1 , wherein the first, second, and third sampling frequencies are between 750 KHz and 8 MHz.

9 . The microphone interface circuit of claim 1 , further comprising an active noise control (ANC) filter coupled between the delta-sigma ADC and the digital lowpass filter, wherein the ANC filter is configured to reduce a group delay distortion of the output of the delta-sigma ADC.

10 . The microphone interface circuit of claim 9 , wherein the ANC filter is a finite impulse response (FIR) filter, the digital lowpass filter is a third order infinite impulse response (IIR) filter, and the digital sigma-delta modulator is a fifth order noise shaper.

11 . The microphone interface circuit of claim 1 , wherein the output of the delta-sigma ADC is a multi-bit data stream, and an output of the digital sigma-delta modulator is a single-bit data stream.

12 . A microphone signal processing method comprising:
converting, by a delta-sigma analog-to-digital converter (ADC), an analog signal to a first digital signal, wherein the delta-sigma ADC is configured to operate at a first sampling frequency; filtering, by a digital lowpass filter, the first digital signal to produce a second digital signal, the digital lowpass filter being configured to operate at a second sampling frequency; and modulating, by a digital sigma-delta modulator, the second digital signal at a third sampling frequency, wherein at least one of the first sampling frequency and the third sampling frequency is higher than the second sampling frequency.

13 . The microphone signal processing method of claim 12 , further comprising:
downsampling, by a digital decimation filter, the first digital signal; and upsampling, by a digital interpolation filter, an output signal of the digital sigma-delta modulator, upsampling comprising repeating each sample of the output signal of the digital sigma-delta modulator a number of times, wherein the first sampling frequency is higher than the second sampling frequency, and the second sampling frequency is equal to the third sampling frequency.

14 . The microphone signal processing method of claim 12 , wherein the digital lowpass filter is a third order infinite impulse response (IIR) filter, and the digital sigma-delta modulator is a fifth order digital sigma-delta modulator.

15 . A microphone interface circuit system comprising:
a Micro-Electro-Mechanical Systems (MEMS) microphone transducer; a delta-sigma analog-to-digital converter (ADC) coupled to an output of the MEMS microphone transducer, the delta-sigma ADC being configured to operate at a first sampling frequency; a digital lowpass filter coupled to an output of the delta-sigma ADC, the digital lowpass filter being configured to operate at a second sampling frequency; a digital sigma-delta modulator coupled to an output of the digital lowpass filter, the digital sigma-delta modulator being configured to operate at a third sampling frequency; and an interface circuit coupled to an output of the digital sigma-delta modulator, wherein at least one of the first sampling frequency and the third sampling frequency is higher than the second sampling frequency.

16 . The microphone interface circuit system of claim 15 , further comprising:
a digital decimation filter coupled between the delta-sigma ADC and the digital lowpass filter; and a digital interpolation filter coupled to the output of the digital sigma-delta modulator, wherein the first sampling frequency is higher than the second sampling frequency, and the second sampling frequency is equal to the third sampling frequency.

17 . The microphone interface circuit system of claim 15 , further comprising:
an active noise control (ANC) filter coupled between the delta-sigma ADC and the digital lowpass filter, the ANC filter reducing a group delay distortion of the output of the delta-sigma ADC.

Assignees

• Infineon Technologies Ag

Inventors

• Bach Elmar
• Straeussnigg Dietmar
• Valli Luca

Classifications

• H03H17/0416

  with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing · CPC title

• H03M3/496 Primary

  Details of sampling arrangements or methods · CPC title

• H03M3/32

  with special provisions or arrangements for power saving, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains, by selectively turning on stages when needed · CPC title

• H04R2201/003

  Mems transducers or their use · CPC title

• H03M3/368

  of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators · CPC title